Design and implementation of a novel multi-constellation FPGA-based dual frequency GNSS receiver for space applications

The PhD activity described in the document is part of the Microsatellite and Microsystem Laboratory of the II Faculty of Engineering, University of Bologna. The main objective is the design and development of a GNSS receiver for the orbit determination of microsatellites in low earth orbit. The development starts from the electronic design and goes up to the implementation of the navigation algorithms, covering all the aspects that are involved in this type of applications. The use of GPS receivers for orbit determination is a consolidated application used in many space missions, but the development of the new GNSS system within few years, such as the European Galileo, the Chinese COMPASS and the Russian modernized GLONASS, proposes new challenges and offers new opportunities to increase the orbit determination performances. The evaluation of improvements coming from the new systems together with the implementation of a receiver that is compatible with at least one of the new systems, are the main activities of the PhD. The activities can be divided in three section: receiver requirements definition and prototype implementation, design and analysis of the GNSS signal tracking algorithms, and design and analysis of the navigation algorithms. The receiver prototype is based on a Virtex FPGA by Xilinx, and includes a PowerPC processor. The architecture follows the software defined radio paradigm, so most of signal processing is performed in software while only what is strictly necessary is done in hardware. The tracking algorithms are implemented as a combination of Phase Locked Loop and Frequency Locked Loop for the carrier, and Delay Locked Loop with variable bandwidth for the code. The navigation algorithm is based on the extended Kalman filter and includes an accurate LEO orbit model.

International Agricultural Trade under Regulatory Asymmetry: An Economic Analysis of SME Export Behavior

Over the last three decades, international agricultural trade has grown significantly. Technological advances in transportation logistics and storage have created opportunities to ship anything almost anywhere. Bilateral and multilateral trade agreements have also opened new pathways to an increasingly global market place. Yet, international agricultural trade is often constrained by differences in regulatory regimes. The impact of “regulatory asymmetry” is particularly acute for small and medium sized enterprises (SMEs) that lack resources and expertise to successfully operate in markets that have substantially different regulatory structures. As governments seek to encourage the development of SMEs, policy makers often confront the critical question of what ultimately motivates SME export behavior. Specifically, there is considerable interest in understanding how SMEs confront the challenges of regulatory asymmetry. Neoclassical models of the firm generally emphasize expected profit maximization under uncertainty, however these approaches do not adequately explain the entrepreneurial decision under regulatory asymmetry. Behavioral theories of the firm offer a far richer understanding of decision making by taking into account aspirations and adaptive performance in risky environments. This paper develops an analytical framework for decision making of a single agent. Considering risk, uncertainty and opportunity cost, the analysis focuses on the export behavior response of an SME in a situation of regulatory asymmetry. Drawing on the experience of fruit processor in Muzaffarpur, India, who must consider different regulatory environments when shipping fruit treated with sulfur dioxide, the study dissects the firm-level decision using @Risk, a Monte Carlo computational tool.

Model predictive control in thermal management of multiprocessor systems-on-chip

MultiProcessor Systems-on-Chip (MPSoC) are the core of nowadays and next generation computing platforms. Their relevance in the global market continuously increase, occupying an important role both in everydaylife products (e.g. smartphones, tablets, laptops, cars) and in strategical market sectors as aviation, defense, robotics, medicine. Despite of the incredible performance improvements in the recent years processors manufacturers have had to deal with issues, commonly called “Walls”, that have hindered the processors development. After the famous “Power Wall”, that limited the maximum frequency of a single core and marked the birth of the modern multiprocessors system-on-chip, the “Thermal Wall” and the “Utilization Wall” are the actual key limiter for performance improvements. The former concerns the damaging effects of the high temperature on the chip caused by the large power densities dissipation, whereas the second refers to the impossibility of fully exploiting the computing power of the processor due to the limitations on power and temperature budgets. In this thesis we faced these challenges by developing efficient and reliable solutions able to maximize performance while limiting the maximum temperature below a fixed critical threshold and saving energy. This has been possible by exploiting the Model Predictive Controller (MPC) paradigm that solves an optimization problem subject to constraints in order to find the optimal control decisions for the future interval. A fully-distributedMPC-based thermal controller with a far lower complexity respect to a centralized one has been developed. The control feasibility and interesting properties for the simplification of the control design has been proved by studying a partial differential equation thermal model. Finally, the controller has been efficiently included in more complex control schemes able to minimize energy consumption and deal with mixed-criticalities tasks

Gpu-based many-core architecture emulation: A double level approach

The efficient emulation of a many-core architecture is a challenging task, each core could be emulated through a dedicated thread and such threads would be interleaved on an either single-core or a multi-core processor. The high number of context switches will results in an unacceptable performance. To support this kind of application, the GPU computational power is exploited in order to schedule the emulation threads on the GPU cores. This presents a non trivial divergence issue, since GPU computational power is offered through SIMD processing elements, that are forced to synchronously execute the same instruction on different memory portions. Thus, a new emulation technique is introduced in order to overcome this limitation: instead of providing a routine for each ISA opcode, the emulator mimics the behavior of the Micro Architecture level, here instructions are date that a unique routine takes as input. Our new technique has been implemented and compared with the classic emulation approach, in order to investigate the chance of a hybrid solution.

Ottimizzazione di protocolli di trasmissione dati tramite interfaccia usb implementati su fpga

La maggior parte dei moderni dispositivi e macchinari, sia ad uso civile che industriale, utilizzano sistemi elettronici che ne supervisionano e ne controllano il funzionamento. All’ interno di questi apparati è quasi certamente impiegato un sistema di controllo digitale che svolge, anche grazie alle potenzialità oggi raggiunte, compiti che fino a non troppi anni or sono erano dominio dell’ elettronica analogica, si pensi ad esempio ai DSP (Digital Signal Processor) oggi impiegati nei sistemi di telecomunicazione. Nonostante l'elevata potenza di calcolo raggiunta dagli odierni microprocessori/microcontrollori/DSP dedicati alle applicazioni embedded, quando è necessario eseguire elaborazioni complesse, time-critical, dovendo razionalizzare e ottimizzare le risorse a disposizione, come ad esempio spazio consumo e costi, la scelta ricade inevitabilmente sui dispositivi FPGA. I dispositivi FPGA, acronimo di Field Programmable Gate Array, sono circuiti integrati a larga scala d’integrazione (VLSI, Very Large Scale of Integration) che possono essere configurati via software dopo la produzione. Si differenziano dai microprocessori poiché essi non eseguono un software, scritto ad esempio in linguaggio assembly oppure in linguaggio C. Sono invece dotati di risorse hardware generiche e configurabili (denominate Configurable Logic Block oppure Logic Array Block, a seconda del produttore del dispositivo) che per mezzo di un opportuno linguaggio, detto di descrizione hardware (HDL, Hardware Description Language) vengono interconnesse in modo da costituire circuiti logici digitali. In questo modo, è possibile far assumere a questi dispositivi funzionalità logiche qualsiasi, non previste in origine dal progettista del circuito integrato ma realizzabili grazie alle strutture programmabili in esso presenti.

Applying the reactive programming paradigm: Toward a more declarative application development approach

After almost 10 years from “The Free Lunch Is Over” article, where the need to parallelize programs started to be a real and mainstream issue, a lot of stuffs did happened: • Processor manufacturers are reaching the physical limits with most of their approaches to boosting CPU performance, and are instead turning to hyperthreading and multicore architectures; • Applications are increasingly need to support concurrency; • Programming languages and systems are increasingly forced to deal well with concurrency. This thesis is an attempt to propose an overview of a paradigm that aims to properly abstract the problem of propagating data changes: Reactive Programming (RP). This paradigm proposes an asynchronous non-blocking approach to concurrency and computations, abstracting from the low-level concurrency mechanisms.

Design of a semi-implantable hearing device for direct acoustic cochlear stimulation

A new hearing therapy based on direct acoustic cochlear stimulation was developed for the treatment of severe to profound mixed hearing loss. The device efficacy was validated in an initial clinical trial with four patients. This semi-implantable investigational device consists of an externally worn audio processor, a percutaneous connector, and an implantable microactuator. The actuator is placed in the mastoid bone, right behind the external auditory canal. It generates vibrations that are directly coupled to the inner ear fluids and that, therefore, bypass the external and the middle ear. The system is able to provide an equivalent sound pressure level of 125 dB over the frequency range between 125 and 8000 Hz. The hermetically sealed actuator is designed to provide maximal output power by keeping its dimensions small enough to enable implantation. A network model is used to simulate the dynamic characteristics of the actuator to adjust its transfer function to the characteristics of the middle ear. The geometry of the different actuator components is optimized using finite-element modeling.

Audiological results with Baha in conductive and mixed hearing loss

The level of improvement in the audiological results of Baha(®) users mainly depends on the patient's preoperative hearing thresholds and the type of Baha sound processor used. This investigation shows correlations between the preoperative hearing threshold and postoperative aided thresholds and audiological results in speech understanding in quiet of 84 Baha users with unilateral conductive hearing loss, bilateral conductive hearing loss and bilateral mixed hearing loss. Secondly, speech understanding in noise of 26 Baha users with different Baha sound processors (Compact, Divino, and BP100) is investigated. Linear regression between aided sound field thresholds and bone conduction (BC) thresholds of the better ear shows highest correlation coefficients and the steepest slope. Differences between better BC thresholds and aided sound field thresholds are smallest for mid-frequencies (1 and 2 kHz) and become larger at 0.5 and 4 kHz. For Baha users, the gain in speech recognition in quiet can be expected to lie in the order of magnitude of the gain in their hearing threshold. Compared to its predecessor sound processors Baha(®) Compact and Baha(®) Divino, Baha(®) BP100 improves speech understanding in noise significantly by +0.9 to +4.6 dB signal-to-noise ratio, depending on the setting and the use of directional microphone. For Baha users with unilateral and bilateral conductive hearing loss and bilateral mixed hearing loss, audiological results in aided sound field thresholds can be estimated with the better BC hearing threshold. The benefit in speech understanding in quiet can be expected to be similar to the gain in their sound field hearing threshold. The most recent technology of Baha sound processor improves speech understanding in noise by an order of magnitude that is well perceived by users and which can be very useful in everyday life.

An integrated environment for filter design

Analog filters and direct digital filters are implemented using digital signal processing techniques. Specifically, Butterworth, Elliptic, and Chebyshev filters are implemented using the Motorola 56001 Digital Signal Processor by the integration of three software packages: MATLAB, C++, and Motorola's Application Development System. The integrated environment allows the novice user to design a filter automatically by specifying the filter order and critical frequencies, while permitting more experienced designers to take advantage of MATLAB's advanced design capabilities. This project bridges the gap between the theoretical results produced by MATLAB and the practicalities of implementing digital filters using the Motorola 56001 Digital Signal Processor. While these results are specific to the Motorola 56001 they may be extended to other digital signal processors. MATLAB handles the filter calculations, a C++ routine handles the conversion to assembly code, and the Motorola software compiles and transmits the code to the processor

Validation of MIPAS IMK/IAA temperature, water vapor, and ozone profiles with MOHAVE-2009 campaign measurements

MIPAS observations of temperature, water vapor, and ozone in October 2009 as derived with the scientific level-2 processor run by Karlsruhe Institute of Technology (KIT), Institute for Meteorology and Climate Research (IMK) and CSIC, Instituto de Astrofísica de Andalucía (IAA) and retrieved from version 4.67 level-1b data have been compared to co-located field campaign observations obtained during the MOHAVE-2009 campaign at the Table Mountain Facility near Pasadena, California in October 2009. The MIPAS measurements were validated regarding any potential biases of the profiles, and with respect to their precision estimates. The MOHAVE-2009 measurement campaign provided measurements of atmospheric profiles of temperature, water vapor/relative humidity, and ozone from the ground to the mesosphere by a suite of instruments including radiosondes, ozonesondes, frost point hygrometers, lidars, microwave radiometers and Fourier transform infra-red (FTIR) spectrometers. For MIPAS temperatures (version V4O_T_204), no significant bias was detected in the middle stratosphere; between 22 km and the tropopause MIPAS temperatures were found to be biased low by up to 2 K, while below the tropopause, they were found to be too high by the same amount. These findings confirm earlier comparisons of MIPAS temperatures to ECMWF data which revealed similar differences. Above 12 km up to 45 km, MIPAS water vapor (version V4O_H2O_203) is well within 10% of the data of all correlative instruments. The well-known dry bias of MIPAS water vapor above 50 km due to neglect of non-LTE effects in the current retrievals has been confirmed. Some instruments indicate that MIPAS water vapor might be biased high by 20 to 40% around 10 km (or 5 km below the tropopause), but a consistent picture from all comparisons could not be derived. MIPAS ozone (version V4O_O3_202) has a high bias of up to +0.9 ppmv around 37 km which is due to a non-identified continuum like radiance contribution. No further significant biases have been detected. Cross-comparison to co-located observations of other satellite instruments (Aura/MLS, ACE-FTS, AIRS) is provided as well.

A Novel Implantable Hearing System with Direct Acoustic Cochlear Stimulation

A new implantable hearing system, the direct acoustic cochlear stimulator (DACS) is presented. This system is based on the principle of a power-driven stapes prosthesis and intended for the treatment of severe mixed hearing loss due to advanced otosclerosis. It consists of an implantable electromagnetic transducer, which transfers acoustic energy directly to the inner ear, and an audio processor worn externally behind the implanted ear. The device is implanted using a specially developed retromeatal microsurgical approach. After removal of the stapes, a conventional stapes prosthesis is attached to the transducer and placed in the oval window to allow direct acoustical coupling to the perilymph of the inner ear. In order to restore the natural sound transmission of the ossicular chain, a second stapes prosthesis is placed in parallel to the first one into the oval window and attached to the patient's own incus, as in a conventional stapedectomy. Four patients were implanted with an investigational DACS device. The hearing threshold of the implanted ears before implantation ranged from 78 to 101 dB (air conduction, pure tone average, 0.5-4 kHz) with air-bone gaps of 33-44 dB in the same frequency range. Postoperatively, substantial improvements in sound field thresholds, speech intelligibility as well as in the subjective assessment of everyday situations were found in all patients. Two years after the implantations, monosyllabic word recognition scores in quiet at 75 dB improved by 45-100 percent points when using the DACS. Furthermore, hearing thresholds were already improved by the second stapes prosthesis alone by 14-28 dB (pure tone average 0.5-4 kHz, DACS switched off). No device-related serious medical complications occurred and all patients have continued to use their device on a daily basis for over 2 years. Copyright (c) 2008 S. Karger AG, Basel.

Nectar distribution and its relation to food quality in honeybee (Apis mellifera) colonies

In honeybees (Apis niellifera), the process of nectar collection is considered a straightforward example of task partitioning with two subtasks or two intersecting cycles of activity: (1) foraging and (2) storing of nectar, linked via its transfer between foragers and food processors. Many observations suggest, however, that nectar colleclion and processing in honeybees is a complex process, involving workers of other sub-castes and depending on variables such as resource profitability or the amount of stored honey. It has been observed that food processor bees often distribute food to other hive bees after receiving it from incoming foragers, instead of storing it immediately in honey cells. While there is little information about the sub-caste affiliation and the behaviour of these second-order receivers, this stage may be important for the rapid distribution of nutrients and related information. To investigate the identity of these second-order receivers, we quantified behaviours following nectar transfer and compared these behaviours with the behaviour of average worker hive-bees. Furthermore, we tested whether food quality (sugar concentration) affects the behaviour of the second-order receivers. Of all identified second-order receivers, 59.3% performed nurse duties, 18.5% performed food-processor duties and 22.2% performed forager duties. After food intake, these bees were more active, had more trophallaxes (especially offering contacts) compared to average workers and they were found mainly in the brood area, independent of food quality. Our results show that the liquid food can be distributed rapidly among many bees of the three main worker sub-castes, without being stored in honey cells first. Furthermore, the results suggest that the rapid distribution of food partly depends on the high activity of second-order receivers.

Design and implementation of a 3D computer game controller using inertial MEMS sensors

Though 3D computer graphics has seen tremendous advancement in the past two decades, most available mechanisms for computer interaction in 3D are high cost and targeted for industry and virtual reality applications. Recent advances in Micro-Electro-Mechanical-System (MEMS) devices have brought forth a variety of new low-cost, low-power, miniature sensors with high accuracy, which are well suited for hand-held devices. In this work a novel design for a 3D computer game controller using inertial sensors is proposed, and a prototype device based on this design is implemented. The design incorporates MEMS accelerometers and gyroscopes from Analog Devices to measure the three components of the acceleration and angular velocity. From these sensor readings, the position and orientation of the hand-held compartment can be calculated using numerical methods. The implemented prototype is utilizes a USB 2.0 compliant interface for power and communication with the host system. A Microchip dsPIC microcontroller is used in the design. This microcontroller integrates the analog to digital converters, the program memory flash, as well as the core processor, on a single integrated circuit. A PC running Microsoft Windows operating system is used as the host machine. Prototype firmware for the microcontroller is developed and tested to establish the communication between the design and the host, and perform the data acquisition and initial filtering of the sensor data. A PC front-end application with a graphical interface is developed to communicate with the device, and allow real-time visualization of the acquired data.

MOWER : A NEW DESIGN FOR NON-BLOCKING MISPREDICTION RECOVERY

Mower is a micro-architecture technique which targets branch misprediction penalties in superscalar processors. It speeds-up the misprediction recovery process by dynamically evicting stale instructions and fixing the RAT (Register Alias Table) using explicit branch dependency tracking. Tracking branch dependencies is accomplished by using simple bit matrices. This low-overhead technique allows overlapping of the recovery process with instruction fetching, renaming and scheduling from the correct path. Our evaluation of the mechanism indicates that it yields performance very close to ideal recovery and provides up to 5% speed-up and 2% reduction in power consumption compared to a traditional recovery mechanism using a reorder buffer and a walker. The simplicity of the mechanism should permit easy implementation of Mower in an actual processor.

Hierarchical Markov Random Fields Applied to Model Soft Tissue Deformations on Graphics Hardware

Many methodologies dealing with prediction or simulation of soft tissue deformations on medical image data require preprocessing of the data in order to produce a different shape representation that complies with standard methodologies, such as mass–spring networks, finite element method s (FEM). On the other hand, methodologies working directly on the image space normally do not take into account mechanical behavior of tissues and tend to lack physics foundations driving soft tissue deformations. This chapter presents a method to simulate soft tissue deformations based on coupled concepts from image analysis and mechanics theory. The proposed methodology is based on a robust stochastic approach that takes into account material properties retrieved directly from the image, concepts from continuum mechanics and FEM. The optimization framework is solved within a hierarchical Markov random field (HMRF) which is implemented on the graphics processor unit (GPU See Graphics processing unit ).