Multifunctional polyether architectures : versatile materials for surface attachment and functionalization

Chapter 1 of this thesis comprises a review of polyether polyamines, i.e., combinations of polyether scaffolds with polymers bearing multiple amino moieties. Focus is laid on controlled or living polymerization methods. Furthermore, fields in which the combination of cationic, complexing, and pH-sensitive properties of the polyamines and biocompatibility and water-solubility of polyethers promise enormous potential are presented. Applications include stimuli-responsive polymers with a lower critical solution temperature (LCST) and/or the ability to gel, preparation of shell cross-linked (SCL) micelles, gene transfection, and surface functionalization.rnIn Chapter 2, multiaminofunctional polyethers relying on the class of glycidyl amine comonomers for anionic ring-opening polymerization (AROP) are presented. In Chapter 2.1, N,N-diethyl glycidyl amine (DEGA) is introduced for copolymerization with ethylene oxide (EO). Copolymer microstructure is assessed using online 1H NMR kinetics, 13C NMR triad sequence analysis, and differential scanning calorimetry (DSC). The concurrent copolymerization of EO and DEGA is found to result in macromolecules with a gradient structure. The LCSTs of the resulting copolymers can be tailored by adjusting DEGA fraction or pH value of the environment. Quaternization of the amino moieties by methylation results in polyelectrolytes. Block copolymers are used for PEGylated gold nanoparticle formation. Chapter 2.2 deals with a glycidyl amine monomer with a removable protecting group at the amino moiety, for liberation of primary amines at the polyether backbone, which is N,N-diallyl glycidyl amine (DAGA). Its allyl groups are able to withstand the harsh basic conditions of AROP, but can be cleaved homogeneously after polymerization. Gradient as well as block copolymers poly(ethylene glycol)-PDAGA (PEG-PDAGA) are obtained. They are analyzed regarding their microstructure, LCST behavior, and cleavage of the protecting groups. rnChapter 3 describes applications of multi(amino)functional polyethers for functionalization of inorganic surfaces. In Chapter 3.1, they are combined with an acetal-protected catechol initiator, leading to well-defined PEG and heteromultifunctional PEG analogues. After deprotection, multifunctional PEG ligands capable of attaching to a variety of metal oxide surfaces are obtained. In a cooperative project with the Department of Inorganic and Analytical Chemistry, JGU Mainz, their potential is demonstrated on MnO nanoparticles, which are promising candidates as T1 contrast agents in magnetic resonance imaging. The MnO nanoparticles are solubilized in aqueous solution upon ligand exchange. In Chapter 3.2, a concept for passivation and functionalization of glass surfaces towards gold nanorods is developed. Quaternized mPEG-b-PqDEGA diblock copolymers are attached to negatively charged glass surfaces via the cationic PqDEGA blocks. The PEG blocks are able to suppress gold nanorod adsorption on the glass in the flow cell, analyzed by dark field microscopy.rnChapter 4 highlights a straightforward approach to poly(ethylene glycol) macrocycles. Starting from commercially available bishydroxy-PEG, cyclic polymers are available by perallylation and ring-closing metathesis in presence of Grubbs’ catalyst. Purification of cyclic PEG is carried out using α-cyclodextrin. This cyclic sugar derivative forms inclusion complexes with remaining unreacted linear PEG in aqueous solution. Simple filtration leads to pure macrocycles, as evidenced by SEC and MALDI-ToF mass spectrometry. Cyclic polymers from biocompatible precursors are interesting materials regarding their increased blood circulation time compared to their linear counterparts.rnIn the Appendix, A.1, a study of the temperature-dependent water-solubility of polyether copolymers is presented. Macroscopic cloud points, determined by turbidimetry, are compared with microscopic aggregation phenomena, monitored by continuous wave electron paramagnetic resonance (CW EPR) spectroscopy in presence of the amphiphilic spin probe and model drug (2,2,6,6-tetramethylpiperidin-1-yl)oxyl (TEMPO). These thermoresponsive polymers are promising candidates for molecular transport applications. The same techniques are applied in Chapter A.2 to explore the pH-dependence of the cloud points of PEG-PDEGA copolymers in further detail. It is shown that the introduction of amino moieties at the PEG backbone allows for precise manipulation of complex phase transition modes. In Chapter A.3, multi-hydroxyfunctional polysilanes are presented. They are obtained via copolymerization of the acetal-protected dichloro(isopropylidene glyceryl propyl ether)methylsilane monomer. The hydroxyl groups are liberated through acidic work-up, yielding versatile access to new multifunctional polysilanes.

Charge generation and recombination in solid-state dye-sensitized solar cells

Diese Doktorarbeit befasst sich mit Ladungsgeneration und – rekombination in Feststoff-Farbstoffsolarzellen, die spiro-OMeTAD als Lochleiter verwenden. Die vorliegende Arbeit ist in drei Fallstudien unterteilt: i.) Kern-erweiterte Rylen-Farbstoffe, ii.) ein Perylenmonoimid-Farbstoff und iii.) Donor-π verbrückte (Cyclopentadithiophen)-Akzeptor-Farbstoffe. Trotz ihres hohen molaren Extinktionskoeffizienten und der hohen Absorbanz der sensibilisierten Filme, zeigen einige dieser Farbstoffmoleküle nur geringe photovoltaischen Effizienzen. Um den Ursprung des geringen Wirkungsgrades herauszufinden, wurde breitbandige, ultraschnelle transiente Absorptionsspektroskopie an Solarzellen durchgeführt.rnInsbesondere die Auswirkungen verschiedender Ankergruppen, Dipolmomente, Photolumineszenzlebenszeiten, Lithium-Kationensensitivität und Ladungsträgerdynamik, die alle einen großen Einfluss auf den Wirkungsgrad der Solarzelle besitzen, wurden untersucht. In der ersten Fallstudie zeigte ein kurzer Rylen-Farbstoff aufgrund deutlich verlängerter Lebenszeiten die beste Effizienz im Vergleich zu größeren Kern-erweiterten Rylen-Farbstoffen. Die Lebenszeit wurde weiter reduziert, wenn Maleinsäure als Ankergruppe unter einer Ringöffnungsreaktion an die mesoporöse Oberfläche des Metalloxid-Halbleiters adsorbierte. Dies konnte mit Hilfe von Berechnungen mittels der Dichtefunktionaltheorie (DFT, B3LYP) auf die Differenz des Dipolmoments zwischen Grundzustand und angeregtem Zustand zurückgeführt werden. Die Berechnungen bekräftigen die unvorteilhafte Injektion von Ladungen durch die Änderung der Richtung des Dipolmoments, wenn eine Ringöffnung der Anhydridgruppe stattfindet. In der zweiten Studie zeigte das Perylenmonoimid-Derivat ID889 einen Wirkungsgrad von 4.5% in Feststoff-Farbstoffsolarzellen, wobei ID889 sogar ohne Zuhilfenahme eines Additivs in der Lage ist langlebige Farbstoffkationen zu bilden. Die Verwendung von Lithium-Kationen stabilisiert jedoch sowohl den Prozess der Ladungsgeneration als auch den der Ladungsregeneration. Des Weiteren wurde in ID889-sensitivierten Bauteilen kein reduktives Löschen beobachtet. Dabei wurde die Dynamik der Exzitonen mittels einer soft-modelling Methode Kurvenanalyse aus den Daten der transienten Absorptionsspektroskopie gewonnen. Zuletzt wurden Strukturen mit Cyclopentadithiophen(CPDT)-Baustein untersucht, die eine typische D-π-A Molekülstruktur bilden. FPH224 und 233 zeigten dabei eine bessere Effizienz als FPH231 und 303 aufgrund einer großen Injektionseffizienz (IE) und längerer Lebenszeit der angeregten Zustände. Dies kann auf reduktives Löschen in FPH231 und 303 zurückgeführt werden, wohingegen FPH224 und 233 einen moderaten Zerfall des Spirokationensignals zeigten.

Reforming dell'etanolo con processo ciclico: studio della reattività di ossidi misti con struttura spinello

This work deals with a study on the feasibility of a new process, aimed at the production of hydrogen from water and ethanol (a compound obtained starting from biomasses), with inherent separation of hydrogen from C-containing products. The strategy of the process includes a first step, during which a metal oxide is contacted with ethanol at high temperature; during this step, the metal oxide is reduced and the corresponding metallic form develops. During the second step, the reduced metal compound is contacted at high temperature with water, to produce molecular hydrogen and with formation of the original metal oxide. In overall, the combination of the two steps within the cycle process corresponds to ethanol reforming, where however COx and H2 are produced separately. Various mixed metal oxides were used as electrons and ionic oxygen carriers, all of them being characterized by the spinel structure typical of M-modified non-stoichiometric ferrites: M0,6Fe2,4O4 (M = Co, Mn or Co/Mn). The first step was investigated in depth; it was found that besides the generation of the expected CO, CO2 and H2O, the products of ethanol anaerobic oxidation, also a large amount of H2 and coke were produced. The latter is highly undesired, since it affects the second step, during which water is fed over the pre-reduced spinel at high temperature. The behavior of the different spinels was affected by the nature of the divalent metal cation. The new materials were tested in terms of both redox proprieties and catalytic activity to generate hydrogen. Still the problem of coke formation remains the greater challenge to solve.

Solar thermal decoupled water electrolysis process I: Proof of concept

A new concept for a solar thermal electrolytic process was developed for the production of H-2 from water. A metal oxide is reduced to a lower oxidation state in air with concentrated solar energy. The reduced oxide is then used either as an anode or solute for the electrolytic production of H-2 in either an aqueous acid or base solution. The presence of the reduced metal oxide as part of the electrolytic cell decreases the potential required for water electrolysis below the ideal 1.23 V required when H-2 and O-2 evolve at 1 bar and 298 K. During electrolysis, H-2 evolves at the cathode at 1 bar while the reduced metal oxide is returned to its original oxidation state, thus completing the H-2 production cycle. Ideal sunlight-to-hydrogen thermal efficiencies were established for three oxide systems: Fe2O3-Fe3O4, Co3O4-CoO, and Mn2O3-Mn3O4. The ideal efficiencies that include radiation heat loss are as high or higher than corresponding ideal values reported in the solar thermal chemistry literature. An exploratory experimental study for the iron oxide system confirmed that the electrolytic and thermal reduction steps occur in a laboratory scale environment.

3CAM - A NOVEL TERNARY CONTENT ADDRESSABLE MEMORY USING THREE-VALUED LOGIC

Content Addressable Memory (CAM) is a special type of Complementary Metal-Oxide-Semiconductor (CMOS) storage element that allows for a parallel search operation on a memory stack in addition to the read and write operations yielded by a conventional SRAM storage array. In practice, it is often desirable to be able to store a “don’t care” state for faster searching operation. However, commercially available CAM chips are forced to accomplish this functionality by having to include two binary memory storage elements per CAM cell,which is a waste of precious area and power resources. This research presents a novel CAM circuit that achieves the “don’t care” functionality with a single ternary memory storage element. Using the recent development of multiple-voltage-threshold (MVT) CMOS transistors, the functionality of the proposed circuit is validated and characteristics for performance, power consumption, noise immunity, and silicon area are presented. This workpresents the following contributions to the field of CAM and ternary-valued logic:• We present a novel Simple Ternary Inverter (STI) transistor geometry scheme for achieving ternary-valued functionality in existing SOI-CMOS 0.18µm processes.• We present a novel Ternary Content Addressable Memory based on Three-Valued Logic (3CAM) as a single-storage-element CAM cell with “don’t care” functionality.• We explore the application of macro partitioning schemes to our proposed 3CAM array to observe the benefits and tradeoffs of architecture design in the context of power, delay, and area.

Tissue-transplant fusion and vascularization of myocardial microtissues and macrotissues implanted into chicken embryos and rats

Cell-based therapies and tissue engineering initiatives are gathering clinical momentum for next-generation treatment of tissue deficiencies. By using gravity-enforced self-assembly of monodispersed primary cells, we have produced adult and neonatal rat cardiomyocyte-based myocardial microtissues that could optionally be vascularized following coating with human umbilical vein endothelial cells (HUVECs). Within myocardial microtissues, individual cardiomyocytes showed native-like cell shape and structure, and established electrochemical coupling via intercalated disks. This resulted in the coordinated beating of microtissues, which was recorded by means of a multi-electrode complementary metal-oxide-semiconductor microchip. Myocardial microtissues (microm3 scale), coated with HUVECs and cast in a custom-shaped agarose mold, assembled to coherent macrotissues (mm3 scale), characterized by an extensive capillary network with typical vessel ultrastructures. Following implantation into chicken embryos, myocardial microtissues recruited the embryo's capillaries to functionally vascularize the rat-derived tissue implant. Similarly, transplantation of rat myocardial microtissues into the pericardium of adult rats resulted in time-dependent integration of myocardial microtissues and co-alignment of implanted and host cardiomyocytes within 7 days. Myocardial microtissues and custom-shaped macrotissues produced by cellular self-assembly exemplify the potential of artificial tissue implants for regenerative medicine.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

COORDINATION CHEMISTRY OF BIS(BENZYL)PHOSPHINATE

The work presented in this dissertation deals with the coordination chemistry of the bis(benzyl)phosphinate ligand with vanadium, tungsten and cobalt. The long term goal of this project was to produce and physically characterize high oxidation state transition metal oxide phosphinate compounds with potential catalytic applications. The reaction of bis(benzyl)phosphinic acid with VO(acac)2 in the presence of water or pyridine leads to the synthesis of trimeric vanadium(IV) clusters (V3(µ3-O)O2)(µ2-O2P(CH2C6H5)2)6(H2O) and (V3(µ3-O)O2)(µ2-O2P(CH2C6H5)2)6(py). In contrast, when diphenylphosphinic acid or 2-hydroxyisophosphindoline-2-oxide were reacted with VO(acac)2, insoluble polymeric compounds were produced. The trimeric clusters were characterized using FTIR, elemental analysis, single crystal diffraction, room temperature magnetic susceptibility, thermogravimetric analysis and differential scanning calorimetry. The variable-temperature, solid-state magnetic susceptibility was measured on (V3(µ3-O)O2)(µ2-O2P(CH2C6H5)2)6(py). The polymeric compounds were characterized using FTIR, powder diffraction and elemental analysis. Two different cubane clusters made of tungsten(V) and vanadium(V) were stabilized using bis(benzyl)phosphinate. The oxidation of (V3(µ3-O)O2)(µ2-O2P(CH2C6H5)2)6(H2O) with tBuOOH led to the formation of V4(µ3-O)4(µ2-O2P(Bn)2)4(O4). W4(µ3-O)4(µ2-O2P(Bn)2)4(O4) was produced by heating W(CO)6 in a 1:1 mixture of EtOH/THF at 120 ˚C. Both compounds were characterized using single crystal diffraction, FTIR, 31P-NMR, 1H-NMR and elemental analysis. W4(µ3-O)4(µ2-O2P(Bn)2)4(O4) was also characterized using UV-vis. Cobalt(II) reacted with bis(benzyl)phosphinate to produce three different dinuclear complexes. [(py)3Co(µ2-O2P(Bn)2)3Co(py)][ClO4], (py)3Co(µ2-O2P(Bn)2)3Co(Cl) and (py)(µ2-NO3)Co(µ2-O2P(Bn)2)3Co(py) were all characterized using single crystal diffraction, elemental analysis and FTIR. Room temperature magnetic susceptibility measurements were performed on [(py)3Co(µ2-O2P(Bn)2)3Co(py)][ClO4] and (py)3Co(µ2-O2P(Bn)2)3Co(Cl). The variable-temperature, solid-state magnetic susceptibility was also measured on [(py)3Co(µ2-O2P(Bn)2)3Co(py)][ClO4].

MULTISCALE EXAMINATION AND MODELING OF ELECTRON TRANSPORT IN NANOSCALE MATERIALS AND DEVICES

For half a century the integrated circuits (ICs) that make up the heart of electronic devices have been steadily improving by shrinking at an exponential rate. However, as the current crop of ICs get smaller and the insulating layers involved become thinner, electrons leak through due to quantum mechanical tunneling. This is one of several issues which will bring an end to this incredible streak of exponential improvement of this type of transistor device, after which future improvements will have to come from employing fundamentally different transistor architecture rather than fine tuning and miniaturizing the metal-oxide-semiconductor field effect transistors (MOSFETs) in use today. Several new transistor designs, some designed and built here at Michigan Tech, involve electrons tunneling their way through arrays of nanoparticles. We use a multi-scale approach to model these devices and study their behavior. For investigating the tunneling characteristics of the individual junctions, we use a first-principles approach to model conduction between sub-nanometer gold particles. To estimate the change in energy due to the movement of individual electrons, we use the finite element method to calculate electrostatic capacitances. The kinetic Monte Carlo method allows us to use our knowledge of these details to simulate the dynamics of an entire device— sometimes consisting of hundreds of individual particles—and watch as a device ‘turns on’ and starts conducting an electric current. Scanning tunneling microscopy (STM) and the closely related scanning tunneling spectroscopy (STS) are a family of powerful experimental techniques that allow for the probing and imaging of surfaces and molecules at atomic resolution. However, interpretation of the results often requires comparison with theoretical and computational models. We have developed a new method for calculating STM topographs and STS spectra. This method combines an established method for approximating the geometric variation of the electronic density of states, with a modern method for calculating spin-dependent tunneling currents, offering a unique balance between accuracy and accessibility.

Dual energy versus single energy MDCT: measurement of radiation dose using adult abdominal imaging protocols

RATIONALE AND OBJECTIVES: The aim of this study was to measure the radiation dose of dual-energy and single-energy multidetector computed tomographic (CT) imaging using adult liver, renal, and aortic imaging protocols. MATERIALS AND METHODS: Dual-energy CT (DECT) imaging was performed on a conventional 64-detector CT scanner using a software upgrade (Volume Dual Energy) at tube voltages of 140 and 80 kVp (with tube currents of 385 and 675 mA, respectively), with a 0.8-second gantry revolution time in axial mode. Parameters for single-energy CT (SECT) imaging were a tube voltage of 140 kVp, a tube current of 385 mA, a 0.5-second gantry revolution time, helical mode, and pitch of 1.375:1. The volume CT dose index (CTDI(vol)) value displayed on the console for each scan was recorded. Organ doses were measured using metal oxide semiconductor field-effect transistor technology. Effective dose was calculated as the sum of 20 organ doses multiplied by a weighting factor found in International Commission on Radiological Protection Publication 60. Radiation dose saving with virtual noncontrast imaging reconstruction was also determined. RESULTS: The CTDI(vol) values were 49.4 mGy for DECT imaging and 16.2 mGy for SECT imaging. Effective dose ranged from 22.5 to 36.4 mSv for DECT imaging and from 9.4 to 13.8 mSv for SECT imaging. Virtual noncontrast imaging reconstruction reduced the total effective dose of multiphase DECT imaging by 19% to 28%. CONCLUSION: Using the current Volume Dual Energy software, radiation doses with DECT imaging were higher than those with SECT imaging. Substantial radiation dose savings are possible with DECT imaging if virtual noncontrast imaging reconstruction replaces precontrast imaging.

Pelagic molybdenum concentration anomalies and the impact of sediment resuspension on the molybdenum budget in two tidal systems of the North Sea

The seasonal dynamics of molybdenum (Mo) were studied in the water column of two tidal basins of the German Wadden Sea (Sylt-Rømø and Spiekeroog) between 2007 and 2011. In contrast to its conservative behaviour in the open ocean, both, losses of more than 50% of the usual concentration level of Mo in seawater and enrichments up to 20% were observed repeatedly in the water column of the study areas. During early summer, Mo removal by adsorption on algae-derived organic matter (e.g. after Phaeocystis blooms) is postulated to be a possible mechanism. Mo bound to organic aggregates is likely transferred to the surface sediment where microbial decomposition enriches Mo in the pore water. First δ98/95Mo data of the study area disclose residual Mo in the open water column being isotopically heavier than MOMo (Mean Ocean Molybdenum) during a negative Mo concentration anomaly, whereas suspended particulate matter shows distinctly lighter values. Based on field observations a Mo isotope enrichment factor of ε = −0.3‰ has been determined which was used to argue against sorption on metal oxide surfaces. It is suggested here that isotope fractionation is caused by biological activity and association to organic matter. Pelagic Mo concentration anomalies exceeding the theoretical salinity-based concentration level, on the other hand, cannot be explained by replenishment via North Sea waters alone and require a supply of excess Mo. Laboratory experiments with natural anoxic tidal flat sediments and modelled sediment displacement during storm events suggest fast and effective Mo release during the resuspension of anoxic sediments in oxic seawater as an important process for a recycling of sedimentary sulphide bound Mo into the water column.

Sediment and pore water geochemistry of sediment cores, Potter Cove, King George Island

Redox-sensitive trace metals (Mn, Fe, U, Mo, Re), nutrients and terminal metabolic products (NO3-, NH4+, PO43-, total alkalinity) were for the first time investigated in pore waters of Antarctic coastal sediments. The results of this study reveal a high spatial variability in redox conditions in surface sediments from Potter Cove, King George Island, western Antarctic Peninsula. Particularly in the shallower areas of the bay the significant correlation between sulphate depletion and total alkalinity, the inorganic product of terminal metabolism, indicates sulphate reduction to be the major pathway of organic matter mineralisation. In contrast, dissimilatory metal oxide reduction seems to be prevailing in the newly ice-free areas and the deeper troughs, where concentrations of dissolved iron of up to 700 µM were found. We suggest that the increased accumulation of fine-grained material with high amounts of reducible metal oxides in combination with the reduced availability of metabolisable organic matter and enhanced physical and biological disturbance by bottom water currents, ice scouring and burrowing organisms favours metal oxide reduction over sulphate reduction in these areas. Based on modelled iron fluxes we calculate the contribution of the Antarctic shelf to the pool of potentially bioavailable iron (Feb) to be 6.9x10**3 to 790x10**3 t/yr. Consequently, these shelf sediments would provide an Feb flux of 0.35-39.5/mg/m**2/yr (median: 3.8 mg/m**2/yr) to the Southern Ocean. This contribution is in the same order of magnitude as the flux provided by icebergs and significantly higher than the input by aeolian dust. For this reason suboxic shelf sediments form a key source of iron for the high nutrient-low chlorophyll (HNLC) areas of the Southern Ocean. This source may become even more important in the future due to rising temperatures at the WAP accompanied by enhanced glacier retreat and the accumulation of melt water derived iron-rich material on the shelf.

Manganese concentrations and flux data of sediments from Broken and Ninetyeast Ridge

Decomposition of organic matter combined with density stratification generate a pronounced intermediate water oxygen minimum zone (OMZ) in the northwest Indian Ocean. This zone currently lies between water depths of 200 and 2000 m and extends approximately 5000 km southeast from the Arabian coast. Based upon benthic foraminiferal assemblage changes, it has been suggested that this OMZ was even more extensive during the late Miocene-early Pliocene (6.5-3.0 Ma), with a maximum volume and/or intensity at approximately 5.0 Ma. While this inference may contribute to an understanding of the history of northwest Indian Ocean upwelling, corroborating geochemical evidence for this interpretation has heretofore been lacking. Ocean Drilling Program (ODP) sites 752, 754, and 757 on Broken and Ninetyeast ridges are located within central Indian Ocean intermediate water depths (1086-1650 m) but outside the present lateral dimensions of the Indian Ocean OMZ. High-resolution chemical analyses of sediment from these sites indicate significant reductions in the flux of Mn and normalized Mn concentrations between 6.5 and 3.0 Ma that are most pronounced at approximately 5.0 Ma. Because late Miocene-Pliocene paleodepths for these sites were essentially the same as at present and because extremely low sedimentation rates (0.3-1.3 cm/ky) most likely precluded sedimentary metal oxide diagenesis, we suggest that the observed Mn depletions reflect diminished deposition of reducible Mn oxyhydroxide phases within O2 deficient intermediate waters and that this effect was most intense at approximately 5.0 Ma. This interpretation implies that waters with less than 2.0 mL/L O2 extended at least 1500 km beyond their present limits and is consistent with changes in benthic foraminifera assemblages. We further suggest this expanded Indian Ocean OMZ is related to regionally and/or globally increased biological productivity.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

CMOS integration of AlN based piezoelectric microcantilevers

El gran crecimiento de los sistemas MEMS (Micro Electro Mechanical Systems) así como su presencia en la mayoría de los dispositivos que usamos diariamente despertó nuestro interés. Paralelamente, la tecnología CMOS (Complementary Metal Oxide Semiconductor) es la tecnología más utilizada para la fabricación de circuitos integrados. Además de ventajas relacionadas con el funcionamiento electrónico del dispositivo final, la integración de sistemas MEMS en la tecnología CMOS reduce significantemente los costes de fabricación. Algunos de los dispositivos MEMS con mayor variedad de aplicaciones son los microflejes. Estos dispositivos pueden ser utilizados para la extracción de energía, en microscopios de fuerza atómica o en sensores, como por ejemplo, para biodetección. Los materiales piezoeléctricos más comúnmente utilizados en aplicaciones MEMS se sintetizan a altas temperaturas y por lo tanto no son compatibles con la tecnología CMOS. En nuestro caso hemos usado nitruro de alumino (AlN), que se deposita a temperatura ambiente y es compatible con la tecnología CMOS. Además, es biocompatible, y por tanto podría formar parte de un dispositivo que actúe como biosensor. A lo largo de esta tesis hemos prestado especial atención en desarrollar un proceso de fabricación rápido, reproducible y de bajo coste. Para ello, todos los pasos de fabricación han sido minuciosamente optimizados. Los parámetros de sputtering para depositar el AlN, las distintas técnicas y recetas de ataque, los materiales que actúan como electrodos o las capas sacrificiales para liberar los flejes son algunos de los factores clave estudiados en este trabajo. Una vez que la fabricación de los microflejes de AlN ha sido optimizada, fueron medidos para caracterizar sus propiedades piezoeléctricas y finalmente verificar positivamente su viabilidad como dispositivos piezoeléctricos. ABSTRACT The huge growth of MEMS (Micro Electro Mechanical Systems) as well as their presence in most of our daily used devices aroused our interest on them. At the same time, CMOS (Complementary Metal Oxide Semiconductor) technology is the most popular technology for integrated circuits. In addition to advantages related with the electronics operation of the final device, the integration of MEMS with CMOS technology reduces the manufacturing costs significantly. Some of the MEMS devices with a wider variety of applications are the microcantilevers. These devices can be used for energy harvesting, in an atomic force microscopes or as sensors, as for example, for biodetection. Most of the piezoelectric materials used for these MEMS applications are synthesized at high temperature and consequently are not compatible with CMOS technology. In our case we have used aluminum nitride (AlN), which is deposited at room temperature and hence fully compatible with CMOS technology. Otherwise, it is biocompatible and and can be used to compose a biosensing device. During this thesis work we have specially focused our attention in developing a high throughput, reproducible and low cost fabrication process. All the manufacturing process steps of have been thoroughly optimized in order to achieve this goal. Sputtering parameters to synthesize AlN, different techniques and etching recipes, electrode material and sacrificial layers are some of the key factors studied in this work to develop the manufacturing process. Once the AlN microcantilevers fabrication was optimized, they were measured to characterize their piezoelectric properties and to successfully check their viability as piezoelectric devices.