A study of frequency response in silicon heterojunction bipolar transistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (aSi:H) is incorporated into a twodimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with aSi:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in aSi:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor. We find that an electron drift mobility of at least 100 cnr'V"'"1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm2 · V1· s1 and heteroemitter doping of 5×1017 cm3, a maximum cutoff frequency of 52 GHz can be expected. © 1996 IEEE.

First-principles prediction of doped graphane as a high-temperature electron-phonon superconductor.

We predict by first-principles calculations that p-doped graphane is an electron-phonon superconductor with a critical temperature above the boiling point of liquid nitrogen. The unique strength of the chemical bonds between carbon atoms and the large density of electronic states at the Fermi energy arising from the reduced dimensionality give rise to a giant Kohn anomaly in the optical phonon dispersions and push the superconducting critical temperature above 90 K. As evidence of graphane was recently reported, and doping of related materials such as graphene, diamond, and carbon nanostructures is well established, superconducting graphane may be feasible.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.