Use of microbial community to evaluate performance of a wetland system in treating Pb/Zn mine drainage

The performance of a wetland system in treating lead (Pb)/zinc (Zn) mine drainage was evaluated by using the polyurethane foam unit (PFU) microbial community (method), which has been adopted by China as a standardized procedure for monitoring water quality. The wetland system consisted of four cells with three dominant plants: Typha latifolia, Phragmites australis and Paspalum distichum. Physicochemical characteristics [pH, EC, content of total suspended solid (TSS) and metals (Pb, Zn, Cd, and Cu)] and PFU microbial community in water samples had been investigated from seven sampling sites. The results indicated that the concentrations of Pb, Zn, Cd, Cu, and TSS in the mine drainage were gradually reduced from the inlet to the outlet of the wetland system and 99%, 98%, 75%, 83%, and 68% of these metals and TSS respectively, had been reduced in concentration after the drainage passed through the wetland system. A total of 105 protozoan species were identified, the number of protozoa species and the diversity index (DI) gradually increased, while the heterotrophic index (HI) gradually decreased from the inlet to the outlet of the wetland system. The results indicated that DI, HI, and total number species of protozoa could be used as biological indicators indicating the improvement of water quality.

Monitoring organochlorine pesticides and polychlorinated biphenyls in Baiyangdian Lake using microbial communities

We used polyurethane foam units (PFUs) to collect persistent organic pollutants (POPs) from four sites in Baiyangdian Lake in July 2003. Following extraction from the PFUs, relative concentrations of seven organochlorine pesticides (OCPs) and ten polychlorinated biphenyls (PCBs) were determined by gas chromatography. OCPs and PCBs were detected in the microbial communities from all the four sampling stations. In terms of the total concentration of POPs (OCPs+ PCBs), two river estuary stations had more POP (18.45 mu g/L and 9.77 mu g/L) than the two mid-lake stations (4.75 mu g/L and 5.21 mu g/L), indicating that Baiyangdian Lake was significantly impacted by inflow from the Fu River and Baigou River.

Root zone microbial populations, urease activities, and purification efficiency for a constructed wetland

In order to investigate the effects of microorganisms and their urease activities in macrophytic root zones on pollutant removal, four small-scale plots (SSPs) of vertical/reverse-vertical flow wetlands were set up to determine: a) the relationship between the abundance of microorganisms in the root zones and water purification efficiency; and b) the relationship between urease activities in the root zones and pollutant removal in a constructed wetland system. Total numbers of the microbial population (bacteria, fungi, and actinomyces) along with urease activities in the macrophytic root zones were determined. In addition, the relationships between microbial populations and urease activities as well as the wastewater purification efficiencies of total phosphorus (TP), total Kjeldahl nitrogen (TKN), biochemical oxygen demand in 5 days (BOD5), and chemical oxygen demand (COD) were also analyzed. The results showed that there was a highly significant positive correlation (r = 0.9772, P < 0.01) between the number of bacteria in the root zones and BOD5 removal efficiency and a significant negative correlation (r = -0.9092, P < 0.05) between the number of fungi and the removal efficiency of TKN. Meanwhile, there was a significant positive correlation (r = 0.8830, P < 0.05) between urease activities in the root zones and the removal efficiency of TKN. Thus, during wastewater treatment in a constructed wetland system, microorganism and urease activities in the root zones were very important factors.

Research progress on algae of the microbial crusts in and and semiarid regions

Microbial crusts are attracting much interest in view of their possible uses in environmental conservation and ecological restoration of the and and semiarid regions. Because algae play an irreplaceable important role in the early formation and the strengthening of microbial crusts, they are paid much more attention to than other cryptogams. In this paper, an overview of the current knowledge on the fine structure and development of microbial crust, focusing on the algal biomass, vertical distribution, succession, influential factors on algae, cohesion of soil stabilization, cementing mechanism for soil particles and the microalgal extracellular polymers is given, with particular emphasis on the authors' researches, and some prospects are put forward as well.

Mitochondrial d-loop sequence variation and phylogeny of gobiobotine fishes

The mitochondrial DNA control region is amplified and sequenced from 8 genera and 10 species of gobiobotine fishes. The phylogenetic tree of Gobiobotinae and some representative species of other Cyprinid subfamilies obtained by the method of neighborhood joining, maximum likelihood and maximum parsimony with Danio rerio as an outgroup indicates that Gobiobotinae fishes are a monophyletic group which is close to Gobioninae subfamily. Gobiobotinae should be included into subfamily Gobioninae in terms of phylogenetic analysis. The research result supports that Gobiobotinae can be divided into genus Xenophysogobio and Gobiobotia. Xenophysogabio is the most primitive genera in the subfamily.

Degenerate four-wave mixing based all-optical wavelength conversion in a semiconductor optical amplifier and highly-nonlinear photonic crystal fiber parametric loop mirror

The idler is separated from the co-propagating pump in a degenerate four-wave mixing (DFWM) with a symmetrical parametric loop mirror (PALM), which is composed of two identical SOAs and a 70 m highly-nonlinear photonic crystal fiber (HN-PCF). The signal and pump are coupled into the symmetrical PALM from different ports, respectively. After the DFWM based wavelength conversion (WC) in the clockwise and anticlockwise, the idler exits from the signal port, while the pump outputs from its input port. Therefore, the pump is effectively suppressed in the idler channel without a high-speed tunable filter. Contrast to a traditional PALM, the DFWM based conversion efficiency is increased greatly, and the functions of the amplification and the WC are integrated in the smart SOA and HN-PCF PALM. (C) 2008 Elsevier B.V. All rights reserved.

Pump-Suppressed Nondegenerate Four-Wave Mixing in a Highly Nonlinear Photonic Crystal Fiber Sagnac Loop

We propose a configuration for suppressing pumps in a broad- and flat-hand tunable nondegenerate four-wave mixing (FWM) wavelength converter. The signal and pumps are coupled into a highly nonlinear photonic crystal fiber symmetrical Sagnac loop. After the FWM wavelength conversion in the loop, the idler is separated from the pumps without a filter. In our experiment, a flat wavelength conversion bandwidth of 36 rim, conversion efficiency of-11 dB., pump-to-signal suppression ratio of 48 dB, and idler-to-pump suppression ratio of 15 dB are achieved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.