Abordagem de construção de arquitetura homogênea para comitês via meta-aprendizagem

In the world we are constantly performing everyday actions. Two of these actions are frequent and of great importance: classify (sort by classes) and take decision. When we encounter problems with a relatively high degree of complexity, we tend to seek other opinions, usually from people who have some knowledge or even to the extent possible, are experts in the problem domain in question in order to help us in the decision-making process. Both the classification process as the process of decision making, we are guided by consideration of the characteristics involved in the specific problem. The characterization of a set of objects is part of the decision making process in general. In Machine Learning this classification happens through a learning algorithm and the characterization is applied to databases. The classification algorithms can be employed individually or by machine committees. The choice of the best methods to be used in the construction of a committee is a very arduous task. In this work, it will be investigated meta-learning techniques in selecting the best configuration parameters of homogeneous committees for applications in various classification problems. These parameters are: the base classifier, the architecture and the size of this architecture. We investigated nine types of inductors candidates for based classifier, two methods of generation of architecture and nine medium-sized groups for architecture. Dimensionality reduction techniques have been applied to metabases looking for improvement. Five classifiers methods are investigated as meta-learners in the process of choosing the best parameters of a homogeneous committee.

Geração automática de hardware apartir de especificações formais: estendendo uma abordagem de tradução

A remoção de inconsistências em um projeto é menos custosa quando realizadas nas etapas iniciais da sua concepção. A utilização de Métodos Formais melhora a compreensão dos sistemas além de possuir diversas técnicas, como a especificação e verificação formal, para identificar essas inconsistências nas etapas iniciais de um projeto. Porém, a transformação de uma especificação formal para uma linguagem de programação é uma tarefa não trivial. Quando feita manualmente, é uma tarefa passível da inserção de erros. O uso de ferramentas que auxiliem esta etapa pode proporcionar grandes benefícios ao produto final a ser desenvolvido. Este trabalho propõe a extensão de uma ferramenta cujo foco é a tradução automática de especificações em CSPm para Handel-C. CSP é uma linguagem de descrição formal adequada para trabalhar com sistemas concorrentes. Handel-C é uma linguagem de programação cujo resultado pode ser compilado diretamente para FPGA's. A extensão consiste no aumento no número de operadores CSPm aceitos pela ferramenta, permitindo ao usuário definir processos locais, renomear canais e utilizar guarda booleana em escolhas externas. Além disto, propomos também a implementação de um protocolo de comunicação que elimina algumas restrições da composição paralela de processos na tradução para Handel-C, permitindo que a comunicação entre múltiplos processos possa ser mapeada de maneira consistente e que a mesma somente ocorra quando for autorizada.

Geração automática de hardware a partir de especificações formais: estendendo uma abordagem de tradução

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Projeto e implementação em FPGA de um processador com conjunto de instrução reconfigurável utilizando VHDL

The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed

Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC

New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the modularity of object-oriented and structured languages such Java, C++ and C. Thus, one can expect that, using AOP, one can improve the understanding of the hardware systems under design, as well as make its components more reusable and easier to maintain. We apply AOP in applications developed using the SystemC library. Several examples will be presented illustrating how to combine AOP and SystemC. During the presentation of these examples, the benefits of this new approach will also be discussed

Um modelo de interconexão de componentes para ambientes mulitmídia distribuídos

Multimedia systems must incorporate middleware concepts in order to abstract hardware and operational systems issues. Applications in those systems may be executed in different kinds of platforms, and their components need to communicate with each other. In this context, it is needed the definition of specific communication mechanisms for the transmission of information flow. This work presents a interconnection component model for distributed multimedia environments, and its implementation details. The model offers specific communication mechanisms for transmission of information flow between software components considering the Cosmos framework requirements in order to support component dynamic reconfiguration

Um modelo de interconexão de componentes para ambientes mulitmídia distribuídos

Multimedia systems must incorporate middleware concepts in order to abstract hardware and operational systems issues. Applications in those systems may be executed in different kinds of platforms, and their components need to communicate with each other. In this context, it is needed the definition of specific communication mechanisms for the transmission of information flow. This work presents a interconnection component model for distributed multimedia environments, and its implementation details. The model offers specific communication mechanisms for transmission of information flow between software components considering the Cosmos framework requirements in order to support component dynamic reconfiguration

Arquitetura deposicional e evolução tectono-estratigráfica das sequências pré-rifte e rifte, na porção central do Vale do Cariri, Bacia do Araripe, NE do Brasil

A complex depositional history, related to Atlantic rifting, demonstrates the geological evolution during the late Jurassic and early Neocomian periods in the Araripe Basin NE Brazil. Based on outcrop, seismic and remote sensing data, a new model of the tectono-stratigraphic evolution of the section that covers the stages Dom João, Rio da Serra and Aratu (Brejo Santo, Missão Velha and Abaiara formations) is presented in this paper. In the stratigraphic section studied, ten sedimentary facies genetically linked to nine architectural elements were described, representing depositional systems associated with fluvial, aeolian and deltaic environments. Based on the relationship between the rates of creation of accommodation space and sediment influx (A / S) it was possible to associate these depositional systems with High and Low accommodation system tracks. These system tracks represent two tectono-sequences, separated by regional unconformities. The Tectono-sequence I, which includes lithotypes from the Brejo Santo Formation and is related to the pre-rift stage, is bounded at the base by the Paleozoic unconformity. This unit represents only a High Accommodation System Track, composed by a succession of pelitic levels interbedded with sandstones and limestones, from a large fluvial floodplain origin, developed under arid climatic conditions. The Tectono-sequence II, separated from the underlying unit by an erosional unconformity, is related to the rift stage, and is composed by the Missão Velha and Abaiara Formation lithotypes. Changes in depositional style that reflect variations in the A / S ratio, and the presence of hydroplastic deformation bands, make it possible to divide this tectonosequence into two internal sequences. Sequence IIA, which includes the lower portion of the Missão Velha Formation and sequence IIB, is composed by the upper section of the Missão Velha and Abaiara Formations The Sequence IIA below, composed only by the Low Accommodation System Track, includes crossbedding sandstones interbedded with massive mudstones, which are interpreted as deposits of sandy gravel beds wandering rivers. Sequence IIB, above, is more complex, showing a basal Low Accommodation System Track and a High Accommodation System Track at the top, separated by an expansion surface. The lower System Track, related to the upper portion of the Missão Velha Formation, is composed by a series of amalgamated channels, separated by erosion surfaces, interpreted as deposits of a belt of braided channels. The High Accommodation System Track, correlated with the Abaiara Unit, is marked by a significant increase in the A / S, resulting in the progradation of a system of braided river deltas with aeolic influence. Regarding tectonic evolution, the stratigraphic study indicates that the Tectonosequence Rift in the Araripe basin was developed in two phases: first characterized by a beginning of rifting, related to Sequence IIA, followed by a phase of syndepositional deformation, represented by sequence IIB. The first phase was not influenced by the development of large faults, but was influenced by a sharp and continuous decrease of accommodation space that permitted a change in depositional patterns, establishing a new depositional architecture. In turn, the stage of syndepositional deformation allowed for the generation of enough accommodation space for the preservation of fluvial-lacustrine deposits and conditioned the progradation of a braided river-dominated delta system.

Arquitetura, litofácies e evolução tectonoestratigráfica da bacia do rio do peixe, nordeste do Brasil

The Rio do Peixe Basin is located in the border of Paraíba and Ceará states, immediately to the north of the Patos shear zone, encompassing an area of 1,315 km2. This is one of the main basins of eocretaceous age in Northeast Brazil, associated to the rifting event that shaped the present continental margin. The basin can be divided into four sub-basins, corresponding to Pombal, Sousa, Brejo das Freiras and Icozinho half-grabens. This dissertation was based on the analysis and interpretation of remote sensing products, field stratigraphic and structural data, and seismic sections and gravity data. Field work detailed the lithofacies characterization of the three formations previously recognised in the basin, Antenor Navarro, Sousa and Rio Piranhas. Unlike the classical vertical stacking, field relations and seismostratigraphic analysis highlighted the interdigitation and lateral equivalency between these units. On bio/chrono-stratigraphic and tectonic grounds, they correlate with the Rift Tectonosequence of neocomian age. The Antenor Navarro Formation rests overlies the crystalline basement in non conformity. It comprises lithofacies originated by a braided fluvial system system, dominated by immature, coarse and conglomeratic sandstones, and polymict conglomerates at the base. Its exposures occur in the different halfgrabens, along its flexural margins. Paleocurrent data indicate source areas in the basement to the north/NW, or input along strike ramps. The Sousa Formation is composed by fine-grained sandstones, siltites and reddish, locally grey-greenish to reddish laminated shales presenting wavy marks, mudcracks and, sometimes, carbonate beds. This formation shows major influence of a fluvial, floodplain system, with seismostratigraphic evidence of lacustrine facies at subsurface. Its distribution occupies the central part of the Sousa and Brejo das Freiras half-grabens, which constitute the main depocenters of the basin. Paleocurrent analysis shows that sediment transport was also from north/NW to south/SE

Definição de requisitos de software baseada numa arquitetura de modelagem de negócios

Não é uma tarefa fácil definir requisitos para os sistemas de software que darão suporte a um negócio, dada a dinâmica de mudanças nos processos. O levantamento de requisitos tem sido feito de forma empírica, sem o apoio de métodos sistematizados que garantam o desenvolvimento baseado nos reais objetivos do negócio. A engenharia de software carece de métodos que tornem mais ordenadas e metódicas as etapas de modelagem de negócios e de levantamento de requisitos de um sistema. Neste artigo é apresentada uma metodologia de desenvolvimento de software resultante da incorporação de atividades propostas para modelagem de negócios e levantamento de requisitos, baseadas em uma arquitetura de modelagem de negócios. Essas atividades tornam o desenvolvimento de software mais sistemático e alinhado aos objetivos da organização, e podem ser incorporadas em qualquer metodologia de desenvolvimento baseada no UP (Unified Process - Processo Unificado).

Avaliação de painéis produzidos a partir de resíduos sólidos para aplicação na arquitetura

O presente trabalho tem por objetivo o reaproveitamento de resíduos sólidos na preparação de painéis para uso na arquitetura. Para atingir as metas propostas, painéis foram preparados a partir de resíduos provenientes de embalagens cartonadas e plásticas, utilizando-se como elemento de reforço, resíduos lignocelulósicos (casca de amendoim e de arroz). A concentração e a natureza dos resíduos utilizados como matriz e como carga foram variadas gerando doze condições experimentais diferentes. As propriedades avaliadas dos painéis foram o módulo de ruptura, módulo de elasticidade, tração perpendicular à superfície, inchamento em espessura, absorção de água e densidade. Todos os ensaios foram realizados segundo as normas ASTM D1037 e EN 317, referente à chapa de partículas. Os resultados foram analisados segundo a norma ANSI A208.1 que especifica as propriedades de desempenho requeridas para as chapas de partículas. Os painéis foram classificados como de baixa densidade, podendo ser utilizados como forros, divisórias, revestimento decorativos e demais aplicações que requerem as mesmas propriedades físicas e mecânicas. Os painéis a base de embalagem plástica reforçados com casca de arroz apresentaram propriedades superiores do que os demais painéis produzidos. O elemento arquitetônico desenvolvido neste estudo representa um novo mercado potencial, podendo ser empregado no ambiente urbano e rural, atendendo ao conceito de produto ecoeficiente.

Estruturas, arquitetura e evolucao do Complexo Granitoide Itaqui (SP)

The Itaqui Granitoid Complex is a drop shaped WNW-ESE trending intrusion with its head' at west. Its contacts with the low-grade metamorphic rocks of the Sao Roque Group are intrusive at west, northwest, north and northeast, and tectonic at south and northeast. The complex is built up by four main intrusive phases which characterize a rising and unroofing process. Petrographically the Itaqui granite comprises five distinct magmatic associations in nine igneous units. -from English summary

Evolvable hardware applied to voice recognition

This paper presents some results of the application on Evolvable Hardware (EHW) in the area of voice recognition. Evolvable Hardware is able to change inner connections, using genetic learning techniques, adapting its own functionality to external condition changing. This technique became feasible by the improvement of the Programmable Logic Devices. Nowadays, it is possible to have, in a single device, the ability to change, on-line and in real-time, part of its own circuit. This work proposes a reconfigurable architecture of a system that is able to receive voice commands to execute special tasks as, to help handicapped persons in their daily home routines. The idea is to collect several voice samples, process them through algorithms based on Mel - Ceptrais theory to obtain their numerical coefficients for each sample, which, compose the universe of search used by genetic algorithm. The voice patterns considered, are limited to seven sustained Portuguese vowel phonemes (a, eh, e, i, oh, o, u).

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.