Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).

The impact of different power dividers used in a non-uniform planar antenna array

Wireless communications are widely used for various applications, requiring antennas with different features. Often, to achieve the desired radiation pattern, is necessary to employ antenna arrays, using non-uniform excitation on its elements. Power dividers can be used and the best known are the T-junction and the Wilkinson power divider, whose main advantage is the isolation between output ports. In this paper the impact of this isolation on the overall performance of a circularly polarized planar antenna array using non-uniform excitation is investigated. Results show a huge decrease of the array bandwidths either in terms of return loss or in polarization, without resistors. © 2014 IEEE.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

Geração automática de controladores em FPGA integrando animação gráfica

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

A shared-disk parallel cluster file system

Dissertação apresentada para obtenção do Grau de Doutor em Informática Pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAs

This paper proposes an online mechanism that can evaluate the sensitivity of single event upsets (SEUs) of field programmable gate arrays (FPGAs). The online detection mechanism cyclically reads and compares the values form the external and internal configuration memories, taking into account the mask information. This remote detection method also signals any mismatch as a result of a SEU that affects both used and not-used FPGA parts, which maximizes the monitored area. By utilizing an external, Web-accessible controller that is connected to the test infrastructure, the possibility of running the same operation in a remote manner is enabled. Moreover, the need for a local memory to store the mask values is also eliminated.

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Credit risk measures: a case of renewable energy companies

The Basel III will have a significant impact on the European banking sector. In September 2010, supervisors of various countries adopted the new rules proposed by the prudential Committee on Banking Supervision to be applied to the business of credit institutions (hereinafter called ICs) in a phased manner from 2013, assuming to its full implementation by 2019. The purpose of this new regulation is to limit the excessive risk that these institutions took on the period preceding the global financial crisis of 2008. This new regulation is known in slang by Basel III. Depending on the requirement of Basel II for banks and their supervisors to assess the soundness and adequacy of internal risk measurement and credit management systems, the development of methodologies for the validation of internal and external evaluation systems is clearly an important issue . More specifically, there is a need to develop tools to validate the systems used to generate the parameters (such as PD, LGD, EAD and ratings of perceived risk) that serve as starting points for the IRB approach for credit risk. In this context, the work is composed of a number of approaches and tools used to evaluate the robustness of these elements IRB systems.

Reliability and availability in reconfigurable computing: a basis for a common solution

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

Evidences for direct magnetic patterning via diffusive transformations using femtosecond laser interferometry

The application of femtosecond laser interferometry to direct patterning of thin-film magnetic alloys is demonstrated. The formation of stripe gratings with submicron periodicities is achieved in Fe1-xVx (x=18-34wt. %) layers, with a difference in magnetic moments up to Delta mu/mu similar to 20 between adjacent stripes but without any significant development of the topographical relief (<1% of the film thickness). The produced gratings exhibit a robust effect of their anisotropy shape on magnetization curves in the film plane. The obtained data witness ultrafast diffusive transformations associated with the process of spinodal decomposition and demonstrate an opportunity for producing magnetic nanostructures with engineered properties upon this basis.

Chaînes opératoires and resource-exploitation strategies in chimpanzee (Pan troglodytes) nut cracking

Journal of Human Evolution, V. 55, pp. 148-163

Estratégia de internacionalização da Grande Porto: seleção, modos de entrada e marketing-mix na abordagem dos mercados internacionais

Dissertação apresentada ao Instituto Politécnico do Porto para obtenção do Grau de Mestre em Gestão das Organizações, Ramo de Gestão de Empresas Orientada pelo Professor Doutor José Freitas Santos

Overproduction, crystallization and preliminary X-ray characterization of Abn2, an endo-1,5-alpha-arabinanase from Bacillus subtilis.

Acta Crystallographica F64 (2008) 636-638

Run-time defragmentation for dynamically reconfigurable hardware

Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.

Algoritmos de estimação da direção de chegada de sinal

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações