Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments

In future systems with relatively unreliable and unpredictable energy sources such as harvesters, the system power supply may become non-deterministic. For energy effective operations, Vdd is an important parameter in any meaningful system control mechanism. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Existing voltage sensing methods are not suitable because they usually require a stable and known reference (voltage, current, time, frequency, etc.), which is difficult to obtain in this environment. This paper describes an autonomous reference-free voltage sensor designed using an asynchronous counter powered by the charge on a capacitor and a small controller. Unlike existing methods, the voltage information is directly generated as a digital code. The sensor, fabricated in the 180 nm technology node, was tested successfully through performing measurements over the voltage range from 1.8 V down to 0.8 V.

NFA decomposition and multiprocessing architecture for parallel regular expression processing

This work presents a novel algorithm for decomposing NFA automata into one-state-active modules for parallel execution on Multiprocessor Systems on Chip (MP-SoC). Furthermore, performance related studies based on a 16-PE system for Snort, Bro and Linux-L7 regular expressions are presented. ©2009 IEEE.

TLM2.0 based timing accurate modeling method for complex NoC systems

Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.

Generalized Selection Combining in Cognitive MIMO Relay Networks

We propose transmit antenna selection with receive generalized selection combining (TAS/GSC) in dual-hop cognitive decode-and-forward (DF) relay networks for reliability enhancement and interference relaxation. In this paradigm, a single antenna which maximizes the receive signal-to-noise ratio (SNR) is selected at the secondary transmitter and a subset of receive antennas with the highest SNRs are combined at the secondary receiver. To demonstrate the impact of multiple primary users on the cognitive relay network, we derive new closed-form expressions for the exact and asymptotic outage probability with TAS/GSC in the secondary network. Several important design insights are reached. We corroborate that the full diversity gain is achieved, which is entirely determined by the total number of antennas in the secondary network. The negative impact of the primary network on the secondary network is reflected in the SNR gain.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.

Holistic Design Strategy for High-Selectivity Low-Loss Integrated Millimetre-Wave Image-Reject Filters

To alleviate practical limitations in the design of mm-wave on-chip image-reject filters, systematic design methodologies are presented. Three low-order filters with high-selectivity and low-loss characteristics are designed and compared. Transmission zeroes are created by means of a quarter-wave transmission line (filter 1) and a series LC resonator (filters 2 and 3). Implemented on SiGe, the filters occupy 0.125, 0.064, and 0.079 mm2 chip area including pads. The measured transmission
losses across 81-86 GHz E-Band frequency range are 3.6-5.2 dB for filter 1, 3.1-4.7 dB for filter 2 and 3.6-5 dB for filter 3 where rejection levels at the image band are greater than 30 dB.

Low Noise Amplifier With Integrated Balanced Antenna for 60 GHz Wireless Communications

The implementation of a dipole antenna co-designed and monolithically integrated with a low noise amplifier (LNA) on low resistivity Si substrate (20 Omega . cm) manufactured in 0.35 mu m commercial SiGe HBT process with f(T)/f(max) of 170 GHz and 250 GHz is investigated theoretically and experimentally. An air gap is introduced between the chip and a reflective ground plane, leading to substantial improvements in efficiency and gain. Moreover, conjugate matching conditions between the antenna and the LNA are exploited, enhancing power transfer between without any additional matching circuit. A prototype is fabricated and tested to validate the performance. The measured 10-dB gain of the standalone LNA is centered at 58 GHz with a die size of 0.7 mm x 0.6 mm including all pads. The simulated results showed antenna directivity of 5.1 dBi with efficiency higher than 70%. After optimization, the co-designed LNA-Antenna chip with a die size of 3 mm x 2.8 mm was characterized in anechoic chamber environment. A maximum gain of higher than 12 dB was obtained.

New androgen receptor genomic targets show an interaction with the ETS1 transcription factor

The androgen receptor (AR) initiates important developmental and oncogenic transcriptional pathways. The AR is known to bind as a homodimer to 15-base pair bipartite palindromic androgen-response elements; however, few direct AR gene targets are known. To identify AR promoter targets, we used chromatin immunoprecipitation with on-chip detection of genomic fragments. We identified 1,532 potential AR-binding sites, including previously known AR gene targets. Many of the new AR target genes show altered expression in prostate cancer. Analysis of sequences underlying AR-binding sites showed that more than 50% of AR-binding sites did not contain the established 15 bp AR-binding element. Unbiased sequence analysis showed 6-bp motifs, which were significantly enriched and were bound directly by the AR in vitro. Binding sequences for the avian erythroblastosis virus E26 homologue (ETS) transcription factor family were also highly enriched, and we uncovered an interaction between the AR and ETS1 at a subset of AR promoter targets.

Pre-Processing Power Traces with a Phase-Sensitive Detector

As cryptographic implementations are increasingly subsumed as functional blocks within larger systems on chip, it becomes more difficult to identify the power consumption signatures of cryptographic operations amongst other unrelated processing activities. In addition, at higher clock frequencies, the current decay between successive processing rounds is only partial, making it more difficult to apply existing pattern matching techniques in side-channel analysis. We show however, through the use of a phase-sensitive detector, that power traces can be pre-processed to generate a filtered output which exhibits an enhanced round pattern, enabling the identification of locations on a device where encryption operations are occurring and also assisting with the re-alignment of power traces for side-channel attacks.

LaGomiCs - Lagomorph Genomics Consortium: An International Collaborative Effort for Sequencing the Genomes of an Entire Mammalian Order

The order Lagomorpha comprises about 90 living species, divided in 2 families: the pikas (Family Ochotonidae), and the rabbits, hares, and jackrabbits (Family Leporidae). Lagomorphs are important economically and scientifically as major human food resources, valued game species, pests of agricultural significance, model laboratory animals, and key elements in food webs. A quarter of the lagomorph species are listed as threatened. They are native to all continents except Antarctica, and occur up to 5000 m above sea level, from the equator to the Arctic, spanning a wide range of environmental conditions. The order has notable taxonomic problems presenting significant difficulties for defining a species due to broad phenotypic variation, overlap of morphological characteristics, and relatively recent speciation events. At present, only the genomes of 2 species, the European rabbit (Oryctolagus cuniculus) and American pika (Ochotona princeps) have been sequenced and assembled. Starting from a paucity of genome information, the main scientific aim of the Lagomorph Genomics Consortium (LaGomiCs), born from a cooperative initiative of the European COST Action “A Collaborative European Network on Rabbit Genome Biology—RGB-Net” and the World Lagomorph Society (WLS), is to provide an international framework for the sequencing of the genome of all extant and selected extinct lagomorphs. Sequencing the genomes of an entire order will provide a large amount of information to address biological problems not only related to lagomorphs but also to all mammals. We present current and planned sequencing programs and outline the final objective of LaGomiCs possible through broad international collaboration.

Characterizing Human Cysticercosis In Portugal

Abstract text Introduction: Cysticercosis results from the ingestion Taenia solium eggs directly by faecal-oral route or contaminated food or water. While, still considered a leading cause of acquired epilepsy in developed countries, this zoonosis has been controlled or eradicated in industrialized countries due to significant improvements in sanitation, pig rearing and slaughterhouse control systems. Objectives: the health burden of human cysticercosis in Portugal. Material and Metodes: We developed a retrospective study on human neurocysticercosis (NCC) hospitalisations based on the national database resulting from National Health Service (NHS) hospital episodes except those of Madeira and Azores Islands. Results: Between 2006 and 2013 there were 357 hospitalized NCC cases in Portugal. Annual frequency of cases between 2006-2013 kept stable (mean 45). NCC was most frequent in those aged 25-34 years (59; 16,5%) and those >75 years (65; 18,2%). Overall, mean age was 47,3 years (median age 45, standard deviation 41,1, mode 28) and 176 cases were in males (49,3%); no significant differences were observed between age and gender (t-student, p>0,05). In Norte Region cases tended to be older than in Lisboa and Vale do Tejo Region. Conclusions: The Directorate-General of Health established the National Observatory of Cysticercosis and Teniiasis which will define criteria for NCC cases monitoring and surveillance (hospitalized and non-hospitalized cases).

Profiles of ageing in the South of Portugal: education and cognitive functioning in elderly persons living in institutionalized and community contexts

The region of the Algarve shows huge differences between the coastline where population in the urban areas grows, and the inland rural areas, in some cases very isolated, which frequently have high ageing indexes. This general scenario, with an elderly population with very different economic and social conditions, frames the ongoing PhD research designed as a cross-sectional study of an intentional sample of elderly persons. The basic theoretical framework departs from the perspective of developmental psychology of life-span and the model of selection, optimisation and compensation for optimal ageing (Baltes & Baltes, 1990; Freund & Baltes, 2002). The present study is a first step in the analysis of empirical data collected in the PhD sample (N=156; age range 65 to 97 years; M = 80.4 years; SD = 7.2 years). Its purpose is to assess the cognitive functioning of participants, screening for cognitive impairment and examine the relations between the cognitive status of the subjects and a number of selected variables including educational level, age, physical activity and living contexts of the subjects. We accessed the cognitive status of the participants with the Portuguese version of Mini Mental State Examination (MMSE) finding a 10.3% prevalence of positive cases with cognitive impairment. The results also show significant relationships between the cognitive status accessed by the MMSE and educational level, professional qualification, age, living arrangement and activity level of the participants. The relationship verified between educational level and cognitive status of the participants was the largest correlation found in the study with the variability in educational level accounting for 44.8% of the variability in MMSE score. This results points in the same direction of several lines of research that corroborate the strong intercorrelation between education and cognitive functioning in old age.

Optimização da lista de células vizinhas em redes LTE

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements