Phase-separation suppression in GaN-rich side of GaNP alloys grown by metal-organic chemical vapor deposition

The GaN-rich side of GaNP ternary alloys has been successfully synthesized by light-radiation heating and low-pressure metal-organic chemical vapor deposition. X-ray diffraction (XRD) rocking curves show that the ( 0002) peak of GaNP shifts to a smaller angle with increasing P content. From the GaNP photoluminescence (PL) spectra, the red shifts from the band-edge emission of GaN are determined to be 73, 78 and 100 meV, respectively, in the GaNP alloys with the P contents of 1.5%, 5.5% and 7.5%. No PL peak or XRD peak related to GaP is observed, indicating that phase separation induced by the short-range distribution of GaP-rich regions in the GaNP layer has been effectively suppressed. The phase-separation suppression in the GaNP layer is associated with the high growth rate and the quick cooling rate under the given growth conditions, which can efficiently restrain the accumulation of P atoms in the GaNP layer.

Radiation hardness improvement of separation-by-implantation-of-oxygen/silicon-on-insulator material by nitrogen ion implantation

In our work, nitrogen ions were implanted into separation-by-implantation-of-oxygen (SIMOX) wafers to improve the radiation hardness of the SIMOX material. The experiments of secondary ion mass spectroscopy (SIMS) analysis showed that some nitrogen ions were distributed in the buried oxide layers and some others were collected at the Si/SiO2 interface after annealing. The results of electron paramagnetic resonance (EPR) suggested the density of the defects in the nitrided samples changed with different nitrogen ion implantation energies. Semiconductor-insulator-semiconductor (SIS) capacitors were made on the materials, and capacitance-voltage (C-V) measurements were carried out to confirm the results. The super total dose radiation tolerance of the materials was verified by the small increase of the drain leakage current of the metal-oxide-semiconductor field effect transistor with n-channel (NMOSFETs) fabricated on the materials before and after total dose irradiation. The optimum implantation energy was also determined.

Lateral phase separation in AlGaN grown on GaN with a high-temperature AIN interlayer

The influences of a high-temperature (HT) AlN interlayer (IL) on the phase separation in crack-free AlGaN grown on GaN have been studied. The depth-dependent cathodoluminescence (CL) spectra indicate a relatively uniform Al distribution in the growth direction, but the monochromatic CL images and the CL spectra obtained by line scan measurements reveal a lateral phase separation in AlGaN grown on relatively thick HT-AlN ILs. Moreover, when increasing the thickness of HT-AlN IL, the domain-like distribution of the AlN mole fraction in AlGaN layers is significantly enhanced through a great reduction of the domain size. The morphology of mesa-like small islands separated by V trenches in the HT-AlN IL, and the grain template formed by the coalescence of these islands during the subsequent AlGaN lateral overgrowth, are attributed to be responsible for the formation of domain-like structures in the AlGaN layer. (c) 2005 American Institute of Physics.

Quantum computation with coupled quantum dots embedded in optical microcavities

Based on an idea that spatial separation of charge states can enhance quantum coherence, we propose a scheme for a quantum computation with the quantum bit (qubit) constructed from two coupled quantum dots. Quantum information is stored in the electron-hole pair state with the electron and hole located in different dots, which enables the qubit state to be very long-lived. Universal quantum gates involving any pair of qubits are realized by coupling the quantum dots through the cavity photon which is a hopeful candidate for the transfer of long-range information. The operation analysis is carried out by estimating the gate time versus the decoherence time.

Photonic switch and NOT logic gate based on the hybrid integration of a GaAsVCSEL and a GaAs MISS

The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators

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A logic for default reasoning

The need to make default assumptions is frequently encountered in reasoning about incompletely specified worlds. Inferences sanctioned by default are best viewed as beliefs which may well be modified or rejected by subsequent observations. It is this property which leads to the non-monotonicity of any logic of defaults. In this paper we propose a logic for default reasoning. We then specialize our treatment to a very large class of commonly occuring defaults. For this class we develop a complete proof theory and show how to interface it with a top down resolution theorem prover. Finally, we provide criteria under which the revision of derived beliefs must be effected.

When is `partial' adequate? A logic-based proof technique using partial specifications

A technique is presented for ascertaining when a (finite-state) partial process specification is adequate, in the sense of being specified enough, for contexts in which it is to be used. The method relies on the automatic generation of a modal formula from the partial specification; if the remainder of the network satisfies this formula, then any process that meets the specification is guaranteed to ensure correct behavior of the overall system. Using the results, the authors develop compositional proof rules for establishing the correctness of networks of parallel processes and illustrate their use with several examples