Hopengarten, Doris, interviewed by Desiree Shayer on January 11, 2009: Audio Part Two

Some themes discussed are: • Colby—enrollment (1) • Colby—dating (2, 5) • Colby—Greek Life (2) • Colby—campus life (2-3, 5,8) • Holidays—Christmas (4) • Colby—student interaction with Waterville Jews (4) • Occupation—economics, psychology (6) • Colby—Winter Carnival (8-9)

Schreider, Judith, interviewed by Desiree Shayer on January 21, 2010: Audio Part Two

Some themes discussed are: • Colby—admissions (2-3) • Colby—dorms (3-4) • Colby—social life (4) • Marriage (4) • Colby—professors (7) • Colby—Dean Runnals (12) • Food—kosher (5) • Dating—rules at Colby (4-5, 6) • Dating—townies (6) • Military service—(8) • Occupation—furniture (8) • Occupation—education (10)

Study of the audio coding algorithm of the MPEG-4 AAC standard and comparison among implementations of modules of the algorithm

Audio coding is used to compress digital audio signals, thereby reducing the amount of bits needed to transmit or to store an audio signal. This is useful when network bandwidth or storage capacity is very limited. Audio compression algorithms are based on an encoding and decoding process. In the encoding step, the uncompressed audio signal is transformed into a coded representation, thereby compressing the audio signal. Thereafter, the coded audio signal eventually needs to be restored (e.g. for playing back) through decoding of the coded audio signal. The decoder receives the bitstream and reconverts it into an uncompressed signal. ISO-MPEG is a standard for high-quality, low bit-rate video and audio coding. The audio part of the standard is composed by algorithms for high-quality low-bit-rate audio coding, i.e. algorithms that reduce the original bit-rate, while guaranteeing high quality of the audio signal. The audio coding algorithms consists of MPEG-1 (with three different layers), MPEG-2, MPEG-2 AAC, and MPEG-4. This work presents a study of the MPEG-4 AAC audio coding algorithm. Besides, it presents the implementation of the AAC algorithm on different platforms, and comparisons among implementations. The implementations are in C language, in Assembly of Intel Pentium, in C-language using DSP processor, and in HDL. Since each implementation has its own application niche, each one is valid as a final solution. Moreover, another purpose of this work is the comparison among these implementations, considering estimated costs, execution time, and advantages and disadvantages of each one.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

LAUDMUS: rumo à implantação e gerenciamento de uma lista de audição musical online

SILVA, Alexandre Reche e. LAUDMUS: rumo à implantação e gerenciamento de uma lista de audição musical online. In: ENCONTRO REGIONAL DA ABEM NORDESTE (Associação Brasileira de Educação Musical), 9, Natal, RN, 2010. Anais eletronicos... Natal, RN, 2010.Trabalho Completo. Disponivel em: . Acesso em: 04 out. 2010.

A novel system for large-scale gene expression analysis: bacterial colonies array

In the present work, we report the use of bacterial colonies to optimize macroarray technique. The devised system is significantly cheaper than other methods available to detect large-scale differential gene expression. Recombinant Escherichia coli clones containing plasmid-encoded copies of 4,608 individual expressed sequence tag (ESTs) were robotically spotted onto nylon membranes that were incubated for 6 and 12 h to allow the bacteria to grow and, consequently, amplify the cloned ESTs. The membranes were then hybridized with a beta-lactamase gene specific probe from the recombinant plasmid and, subsequently, phosphorimaged to quantify the microbial cells. Variance analysis demonstrated that the spot hybridization signal intensity was similar for 3,954 ESTs (85.8%) after 6 h of bacterial growth. Membranes spotted with bacteria colonies grown for 12 h had 4,017 ESTs (87.2%) with comparable signal intensity but the signal to noise ratio was fivefold higher. Taken together, the results of this study indicate that it is possible to investigate large-scale gene expression using macroarrays based on bacterial colonies grown for 6 h onto membranes.

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

Projeto em FPGA de um controlador unificado para correção de fator de potência em retificadores boost bidirecionais monofásicos

The use of Field Programmable Gate Array (FPGA) for development of digital control strategies for power electronics applications has aroused a growing interest of many researchers. This interest is due to the great advantages offered by FPGA, which include: lower design effort, high performance and highly flexible prototyping. This work proposes the development and implementation of an unified one-cycle controller for boost CFP rectifier based on FPGA. This controller can be applied to a total of twelve converters, six inverters and six rectifiers defined by four single phase VSI topologies and three voltage modulation types. The topologies considered in this work are: full-bridge, interleaved full-bridge, half-bridge and interleaved half-bridge. While modulations are classified in bipolar voltage modulation (BVM), unipolar voltage modulation (UVM) and clamped voltage modulation (CVM). The proposed project is developed and prototyped using tools Matlab/Simulink® together with the DSP Builder library provided by Altera®. The proposed controller was validated with simulation and experimental results

Sensor array made with nanostructured films to detect a phenothiazine compound

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Fibroblast functionality on novel Ti-30Ta nanotube array

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)