El impuesto al latifundio en la provincia de Buenos Aires durante las décadas de 1940 y 1950

El propósito de este artículo es el estudio del proceso de gravamen sobre el latifundio durante las décadas de 1940 y 1950 como parte de un conjunto de políticas agrarias en torno a la propiedad y tenencia de la tierra (arrendamientos y colonización) que contemplan los niveles de producción, de acumulación y la distribución del ingreso en función de controlar el orden social y asegurar la legitimidad del poder político; articulado con el análisis de las resonancias y respuestas de las corporaciones de grandes propietarios en los contextos específicos, lo que permite una aprehensión más integral de la naturaleza y desempeño de esta clase social rural.

Pollen record and calculated holocene vegetation and climate dynamics from Sihailongwan Maar Lake, NE China

High-resolution palynological analysis on annually laminated sediments of Sihailongwan Maar Lake (SHL) provides new insights into the Holocene vegetation and climate dynamics of NE China. The robust chronology of the presented record is based on varve counting and AMS radiocarbon dates from terrestrial plant macro-remains. In addition to the qualitative interpretation of the pollen data, we provide quantitative reconstructions of vegetation and climate based on the method of biomization and weighted averaging partial least squares regression (WA-PLS) technique, respectively. Power spectra were computed to investigate the frequency domain distribution of proxy signals and potential natural periodicities. Pollen assemblages, pollen-derived biome scores and climate variables as well as the cyclicity pattern indicate that NE China experienced significant changes in temperature and moisture conditions during the Holocene. Within the earliest phase of the Holocene, a large-scale reorganization of vegetation occurred, reflecting the reconstructed shift towards higher temperatures and precipitation values and the initial Holocene strengthening and northward expansion of the East Asian summer monsoon (EASM). Afterwards, summer temperatures remain at a high level, whereas the reconstructed precipitation shows an increasing trend until approximately 4000 cal. yr BP. Since 3500 cal. yr BP, temperature and precipitation values decline, indicating moderate cooling and weakening of the EASM. A distinct periodicity of 550-600 years and evidence of a Mid-Holocene transition from a temperature-triggered to a predominantly moisture-triggered climate regime are derived from the power spectra analysis. The results obtained from SHL are largely consistent with other palaeoenvironmental records from NE China, substantiating the regional nature of the reconstructed vegetation and climate patterns. However, the reconstructed climate changes contrast with the moisture evolution recorded in S China and the mid-latitude (semi-)arid regions of N China. Whereas a clear insolation-related trend of monsoon intensity over the Holocene is lacking from the SHL record, variations in the coupled atmosphere-Pacific Ocean system can largely explain the reconstructed changes in NE China.

Pore depth evolution of a pyrochlore pellet

The long-term stability of ceramic materials that are considered as potential nuclear waste forms is governed by heterogeneous surface reactivity. Thus, instead of a mean rate, the identification of one or more dominant contributors to the overall dissolution rate is the key to predict the stability of waste forms quantitatively. Direct surface measurements by vertical scanning interferometry (VSI) and their analysis via material flux maps and resulting dissolution rate spectra provide data about dominant rate contributors and their variability over time. Using pyrochlore (Nd2Zr2O7) pellet dissolution under acidic conditions as an example, we demonstrate the identification and quantification of dissolution rate contributors, based on VSI data and rate spectrum analysis. Heterogeneous surface alteration of pyrochlore varies by a factor of about 5 and additional material loss by chemo-mechanical grain pull-out within the uppermost grain layer. We identified four different rate contributors that are responsible for the observed dissolution rate range of single grains. Our new concept offers the opportunity to increase our mechanistic understanding and to predict quantitatively the alteration of ceramic waste forms.

Tether radiation in Juno-type and circular-equatorial Jovian orbits

Wave radiation by a conductor carrying a steady current in both a polar, highly eccentric, low perijove orbit, as in NASA's planned Juno mission, and an equatorial low Jovian orbit (LJO) mission below the intense radiation belts, is considered. Both missions will need electric power generation for scientific instruments and communication systems. Tethers generate power more efficiently than solar panels or radioisotope power systems (RPS). The radiation impedance is required to determine the current in the overall tether circuit. In a cold plasma model, radiation occurs mainly in the Alfven and fast magnetosonic modes, exhibiting a large refraction index. The radiation impedance of insulated tethers is determined for both modes and either mission. Unlike the Earth ionospheric case, the low-density, highly magnetized Jovian plasma makes the electron gyrofrequency much larger than the plasma frequency; this substantially modifies the power spectrum for either mode by increasing the Alfven velocity. Finally, an estimation of the radiation impedance of bare tethers is considered. In LJO, a spacecraft orbiting in a slow downward spiral under the radiation belts would allow determining magnetic field structure and atmospheric composition for understanding the formation, evolution, and structure of Jupiter. Additionally, if the cathodic contactor is switched off, a tether floats electrically, allowing e-beam emission that generate auroras. On/off switching produces bias/current pulses and signal emission, which might be used for Jovian plasma diagnostics.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Contribución al diseño de lazos de realimentación electrónica para microsistemas electromecánicos (MEMS) resonantes: ruido de fase generado en lazos osciladores por sus realimentaciones

En 1966, D. B. Leeson publicó el artículo titulado “A simple model of feedback oscillator noise spectrum” en el que, mediante una ecuación obtenida de forma heurística y basada en parámetros conocidos de los osciladores, proponía un modelo para estimar el espectro de potencia que cuantifica el Ruido de Fase de estos osciladores. Este Ruido de Fase pone de manifiesto las fluctuaciones aleatorias que se producen en la fase de la señal de salida de cualquier oscilador de frecuencia f_0. Desde entonces, los adelantos tecnológicos han permitido grandes progresos en cuanto a la medida del Ruido de Fase, llegando a encontrar una estrecha “zona plana”, alrededor de f_0, conocida con el nombre de Ensanchamiento de Línea (EL) que Leeson no llegó a observar y que su modelo empírico no recogía. Paralelamente han ido surgiendo teorías que han tratado de explicar el Ruido de Fase con mayor o menor éxito. En esta Tesis se propone una nueva teoría para explicar el espectro de potencia del Ruido de Fase de un oscilador realimentado y basado en resonador L-C (Inductancia-Capacidad). Al igual que otras teorías, la nuestra también relaciona el Ruido de Fase del oscilador con el ruido térmico del circuito que lo implementa pero, a diferencia de aquellas, nuestra teoría se basa en un Modelo Complejo de ruido eléctrico que considera tanto las Fluctuaciones de energía eléctrica asociadas a la susceptancia capacitiva del resonador como las Disipaciones de energía eléctrica asociadas a su inevitable conductancia G=1⁄R, que dan cuenta del contacto térmico entre el resonador y el entorno térmico que le rodea. En concreto, la nueva teoría que proponemos explica tanto la parte del espectro del Ruido de Fase centrada alrededor de la frecuencia portadora f_0 que hemos llamado EL y su posterior caída proporcional a 〖∆f〗^(-2) al alejarnos de f_0, como la zona plana o pedestal que aparece en el espectro de Ruido de Fase lejos de esa f_0. Además, al saber cuantificar el EL y su origen, podemos explicar con facilidad la aparición de zonas del espectro de Ruido de Fase con caída 〖∆f〗^(-3) cercanas a la portadora y que provienen del denominado “exceso de ruido 1⁄f” de dispositivos de Estado Sólido y del ruido “flicker” de espectro 1⁄f^β (0,8≤β≤1,2) que aparece en dispositivos de vacío como las válvulas termoiónicas. Habiendo mostrado que una parte del Ruido de Fase de osciladores L-C realimentados que hemos denominado Ruido de Fase Térmico, se debe al ruido eléctrico de origen térmico de la electrónica que forma ese oscilador, proponemos en esta Tesis una nueva fuente de Ruido de Fase que hemos llamado Ruido de Fase Técnico, que se añadirá al Térmico y que aparecerá cuando el desfase del lazo a la frecuencia de resonancia f_0 del resonador no sea 0° o múltiplo entero de 360° (Condición Barkhausen de Fase, CBF). En estos casos, la modulación aleatoria de ganancia de lazo que realiza el Control Automático de Amplitud en su lucha contra ruidos que traten de variar la amplitud de la señal oscilante del lazo, producirá a su vez una modulación aleatoria de la frecuencia de tal señal que se observará como más Ruido de Fase añadido al Térmico. Para dar una prueba empírica sobre la existencia de esta nueva fuente de Ruido de Fase, se diseñó y construyó un oscilador en torno a un resonador mecánico “grande” para tener un Ruido de Fase Térmico despreciable a efectos prácticos. En este oscilador se midió su Ruido de Fase Técnico tanto en función del valor del desfase añadido al lazo de realimentación para apartarlo de su CBF, como en función de la perturbación de amplitud inyectada para mostrar sin ambigüedad la aparición de este Ruido de Fase Técnico cuando el lazo tiene este fallo técnico: que no cumple la Condición Barkhausen de Fase a la frecuencia de resonancia f_0 del resonador, por lo que oscila a otra frecuencia. ABSTRACT In 1966, D. B. Leeson published the article titled “A simple model of feedback oscillator noise spectrum” in which, by means of an equation obtained heuristically and based on known parameters of the oscillators, a model was proposed to estimate the power spectrum that quantifies the Phase Noise of these oscillators. This Phase Noise reveals the random fluctuations that are produced in the phase of the output signal from any oscillator of frequencyf_0. Since then, technological advances have allowed significant progress regarding the measurement of Phase Noise. This way, the narrow flat region that has been found around f_(0 ), is known as Line Widening (LW). This region that Leeson could not detect at that time does not appear in his empirical model. After Leeson’s work, different theories have appeared trying to explain the Phase Noise of oscillators. This Thesis proposes a new theory that explains the Phase Noise power spectrum of a feedback oscillator around a resonator L-C (Inductance-Capacity). Like other theories, ours also relates the oscillator Phase Noise to the thermal noise of the feedback circuitry, but departing from them, our theory uses a new, Complex Model for electrical noise that considers both Fluctuations of electrical energy associated with the capacitive susceptance of the resonator and Dissipations of electrical energy associated with its unavoidable conductance G=1/R, which accounts for the thermal contact between the resonator and its surrounding environment (thermal bath). More specifically, the new theory we propose explains both the Phase Noise region of the spectrum centered at the carrier frequency f_0 that we have called LW and shows a region falling as 〖∆f〗^(-2) as we depart from f_0, and the flat zone or pedestal that appears in the Phase Noise spectrum far from f_0. Being able to quantify the LW and its origin, we can easily explain the appearance of Phase Noise spectrum zones with 〖∆f〗^(-3) slope near the carrier that come from the so called “1/f excess noise” in Solid-State devices and “flicker noise” with 1⁄f^β (0,8≤β≤1,2) spectrum that appears in vacuum devices such as thermoionic valves. Having shown that the part of the Phase Noise of L-C oscillators that we have called Thermal Phase Noise is due to the electrical noise of the electronics used in the oscillator, this Thesis can propose a new source of Phase Noise that we have called Technical Phase Noise, which will appear when the loop phase shift to the resonance frequency f_0 is not 0° or an integer multiple of 360° (Barkhausen Phase Condition, BPC). This Phase Noise that will add to the Thermal one, comes from the random modulation of the loop gain carried out by the Amplitude Automatic Control fighting against noises trying to change the amplitude of the oscillating signal in the loop. In this case, the BPC failure gives rise to a random modulation of the frequency of the output signal that will be observed as more Phase Noise added to the Thermal one. To give an empirical proof on the existence of this new source of Phase Noise, an oscillator was designed and constructed around a “big” mechanical resonator whose Thermal Phase Noise is negligible for practical effects. The Technical Phase Noise of this oscillator has been measured with regard to the phase lag added to the feedback loop to separate it from its BPC, and with regard to the amplitude disturbance injected to show without ambiguity the appearance of this Technical Phase Noise that appears when the loop has this technical failure: that it does not fulfill the Barkhausen Phase Condition at f_0, the resonance frequency of the resonator and therefore it is oscillating at a frequency other than f_0.

Nonlinear seismic behaviour of concrete arch bridges

Arch bridge structural solution has been known for centuries, in fact the simple nature of arch that require low tension and shear strength was an advantage as the simple materials like stone and brick were the only option back in ancient centuries. By the pass of time especially after industrial revolution, the new materials were adopted in construction of arch bridges to reach longer spans. Nowadays one long span arch bridge is made of steel, concrete or combination of these two as "CFST", as the result of using these high strength materials, very long spans can be achieved. The current record for longest arch belongs to Chaotianmen bridge over Yangtze river in China with 552 meters span made of steel and the longest reinforced concrete type is Wanxian bridge which also cross the Yangtze river through a 420 meters span. Today the designer is no longer limited by span length as long as arch bridge is the most applicable solution among other approaches, i.e. cable stayed and suspended bridges are more reasonable if very long span is desired. Like any super structure, the economical and architectural aspects in construction of a bridge is extremely important, in other words, as a narrower bridge has better appearance, it also require smaller volume of material which make the design more economical. Design of such bridge, beside the high strength materials, requires precise structural analysis approaches capable of integrating the combination of material behaviour and complex geometry of structure and various types of loads which may be applied to bridge during its service life. Depend on the design strategy, analysis may only evaluates the linear elastic behaviour of structure or consider the nonlinear properties as well. Although most of structures in the past were designed to act in their elastic range, the rapid increase in computational capacity allow us to consider different sources of nonlinearities in order to achieve a more realistic evaluations where the dynamic behaviour of bridge is important especially in seismic zones where large movements may occur or structure experience P - _ effect during the earthquake. The above mentioned type of analysis is computationally expensive and very time consuming. In recent years, several methods were proposed in order to resolve this problem. Discussion of recent developments on these methods and their application on long span concrete arch bridges is the main goal of this research. Accordingly available long span concrete arch bridges have been studied to gather the critical information about their geometrical aspects and properties of their materials. Based on concluded information, several concrete arch bridges were designed for further studies. The main span of these bridges range from 100 to 400 meters. The Structural analysis methods implemented in in this study are as following: Elastic Analysis: Direct Response History Analysis (DRHA): This method solves the direct equation of motion over time history of applied acceleration or imposed load in linear elastic range. Modal Response History Analysis (MRHA): Similar to DRHA, this method is also based on time history, but the equation of motion is simplified to single degree of freedom system and calculates the response of each mode independently. Performing this analysis require less time than DRHA. Modal Response Spectrum Analysis (MRSA): As it is obvious from its name, this method calculates the peak response of structure for each mode and combine them using modal combination rules based on the introduced spectra of ground motion. This method is expected to be fastest among Elastic analysis. Inelastic Analysis: Nonlinear Response History Analysis (NL-RHA): The most accurate strategy to address significant nonlinearities in structural dynamics is undoubtedly the nonlinear response history analysis which is similar to DRHA but extended to inelastic range by updating the stiffness matrix for every iteration. This onerous task, clearly increase the computational cost especially for unsymmetrical buildings that requires to be analyzed in a full 3D model for taking the torsional effects in to consideration. Modal Pushover Analysis (MPA): The Modal Pushover Analysis is basically the MRHA but extended to inelastic stage. After all, the MRHA cannot solve the system of dynamics because the resisting force fs(u; u_ ) is unknown for inelastic stage. The solution of MPA for this obstacle is using the previously recorded fs to evaluate system of dynamics. Extended Modal Pushover Analysis (EMPA): Expanded Modal pushover is a one of very recent proposed methods which evaluates response of structure under multi-directional excitation using the modal pushover analysis strategy. In one specific mode,the original pushover neglect the contribution of the directions different than characteristic one, this is reasonable in regular symmetric building but a structure with complex shape like long span arch bridges may go through strong modal coupling. This method intend to consider modal coupling while it take same time of computation as MPA. Coupled Nonlinear Static Pushover Analysis (CNSP): The EMPA includes the contribution of non-characteristic direction to the formal MPA procedure. However the static pushovers in EMPA are performed individually for every mode, accordingly the resulted values from different modes can be combined but this is only valid in elastic phase; as soon as any element in structure starts yielding the neutral axis of that section is no longer fixed for both response during the earthquake, meaning the longitudinal deflection unavoidably affect the transverse one or vice versa. To overcome this drawback, the CNSP suggests executing pushover analysis for governing modes of each direction at the same time. This strategy is estimated to be more accurate than MPA and EMPA, moreover the calculation time is reduced because only one pushover analysis is required. Regardless of the strategy, the accuracy of structural analysis is highly dependent on modelling and numerical integration approaches used in evaluation of each method. Therefore the widely used Finite Element Method is implemented in process of all analysis performed in this research. In order to address the study, chapter 2, starts with gathered information about constructed long span arch bridges, this chapter continuous with geometrical and material definition of new models. Chapter 3 provides the detailed information about structural analysis strategies; furthermore the step by step description of procedure of all methods is available in Appendix A. The document ends with the description of results and conclusion of chapter 4.

The microwave background anisotropies: Observations

Most cosmologists now believe that we live in an evolving universe that has been expanding and cooling since its origin about 15 billion years ago. Strong evidence for this standard cosmological model comes from studies of the cosmic microwave background radiation (CMBR), the remnant heat from the initial fireball. The CMBR spectrum is blackbody, as predicted from the hot Big Bang model before the discovery of the remnant radiation in 1964. In 1992 the cosmic background explorer (COBE) satellite finally detected the anisotropy of the radiation—fingerprints left by tiny temperature fluctuations in the initial bang. Careful design of the COBE satellite, and a bit of luck, allowed the 30 μK fluctuations in the CMBR temperature (2.73 K) to be pulled out of instrument noise and spurious foreground emissions. Further advances in detector technology and experiment design are allowing current CMBR experiments to search for predicted features in the anisotropy power spectrum at angular scales of 1° and smaller. If they exist, these features were formed at an important epoch in the evolution of the universe—the decoupling of matter and radiation at a temperature of about 4,000 K and a time about 300,000 years after the bang. CMBR anisotropy measurements probe directly some detailed physics of the early universe. Also, parameters of the cosmological model can be measured because the anisotropy power spectrum depends on constituent densities and the horizon scale at a known cosmological epoch. As sophisticated experiments on the ground and on balloons pursue these measurements, two CMBR anisotropy satellite missions are being prepared for launch early in the next century.

Temporal fluctuations in coherence of brain waves.

As a measure of dynamical structure, short-term fluctuations of coherence between 0.3 and 100 Hz in the electroencephalogram (EEG) of humans were studied from recordings made by chronic subdural macroelectrodes 5-10 mm apart, on temporal, frontal, and parietal lobes, and from intracranial probes deep in the temporal lobe, including the hippocampus, during sleep, alert, and seizure states. The time series of coherence between adjacent sites calculated every second or less often varies widely in stability over time; sometimes it is stable for half a minute or more. Within 2-min samples, coherence commonly fluctuates by a factor up to 2-3, in all bands, within the time scale of seconds to tens of seconds. The power spectrum of the time series of these fluctuations is broad, extending to 0.02 Hz or slower, and is weighted toward the slower frequencies; little power is faster than 0.5 Hz. Some records show conspicuous swings with a preferred duration of 5-15s, either irregularly or quasirhythmically with a broad peak around 0.1 Hz. Periodicity is not statistically significant in most records. In our sampling, we have not found a consistent difference between lobes of the brain, subdural and depth electrodes, or sleeping and waking states. Seizures generally raise the mean coherence in all frequencies and may reduce the fluctuations by a ceiling effect. The coherence time series of different bands is positively correlated (0.45 overall); significant nonindependence extends for at least two octaves. Coherence fluctuations are quite local; the time series of adjacent electrodes is correlated with that of the nearest neighbor pairs (10 mm) to a coefficient averaging approximately 0.4, falling to approximately 0.2 for neighbors-but-one (20 mm) and to < 0.1 for neighbors-but-two (30 mm). The evidence indicates fine structure in time and space, a dynamic and local determination of this measure of cooperativity. Widely separated frequencies tending to fluctuate together exclude independent oscillators as the general or usual basis of the EEG, although a few rhythms are well known under special conditions. Broad-band events may be the more usual generators. Loci only a few millimeters apart can fluctuate widely in seconds, either in parallel or independently. Scalp EEG coherence cannot be predicted from subdural or deep recordings, or vice versa, and intracortical microelectrodes show still greater coherence fluctuation in space and time. Widely used computations of chaos and dimensionality made upon data from scalp or even subdural or depth electrodes, even when reproducible in successive samples, cannot be considered representative of the brain or the given structure or brain state but only of the scale or view (receptive field) of the electrodes used. Relevant to the evolution of more complex brains, which is an outstanding fact of animal evolution, we believe that measures of cooperativity are likely to be among the dynamic features by which major evolutionary grades of brains differ.

Síntese de óxidos metálicos binários suportados em carbono amorfo (printex 6L) para a produção eletroquímica de peróxido de hidrogênio (H2O2)

O presente trabalho visa o estudo da eletrossíntese de H2O2 a partir da reação de redução de oxigênio (RRO) utilizando carbono Printex 6L modificado com óxidos binários compostos de nióbio, molibdênio e paládio, síntetizados pelo método dos precursores poliméricos. A análise dos materiais preparados foi feita a partir de experimentos de análise termogravimétrica (do inglês, TGA), fluorescência de raios X (FRX) e também de difração de raios X (DRX). As temperaturas de síntese foram escolhidas a partir dos resultados de TGA e tendo como temperatura máxima de 400 °C. As análises dos espectros de emissão de FRX mostraram a eficiência na incorporação dos materiais na matriz de carbono. Experimentos de DRX mostraram a presença de fases cristalinas de MoO2 e Nb2 O5 e PdO, e em comparação aos resultados da técnica de voltametria cíclica, existem pares redox que podem ser associados as transições dos metais nos estados de oxidação de +4 e +5, para molibdênio e nióbio, respectivamente e do estado +2 para o paládio. Nos experimentos de voltametria de varredura linear pode-se observar a tendência de maior geração de H2O2 pelo material com teor de 1% NbMo quando comparado com o carbono Printex 6L, de modo que foram calculadas as eficiências de geração de H2O2 , obtendo um resultado de 55,5% para o modificador de 1% NbMo comparado com 47,4% para o Printex 6L, e também de número de elétrons envolvidos na reação com um valor de 2,9 para o material de 1% e 3,1 para o carbono Printex. As análises das curvas de Koutechy-Levich confirmam os resultados anteriores. Análises em condições reduzidas na síntese orgânica corroboraram a melhor eficiência do material de 1% para o material com nióbio e molibdênio e revelaram a também a melhora eletrocatalítica do carbono quando incorporado com óxidos mistos de nióbio e paládio, sendo o melhor resultado expresso no material contendo 5% de nióbio e paládio, na proporção molar de 95 para 5% de cada elemento, respectivamente.

Method for targetless tracking subpixel in-plane movements

We present a targetless motion tracking method for detecting planar movements with subpixel accuracy. This method is based on the computation and tracking of the intersection of two nonparallel straight-line segments in the image of a moving object in a scene. The method is simple and easy to implement because no complex structures have to be detected. It has been tested and validated using a lab experiment consisting of a vibrating object that was recorded with a high-speed camera working at 1000 fps. We managed to track displacements with an accuracy of hundredths of pixel or even of thousandths of pixel in the case of tracking harmonic vibrations. The method is widely applicable because it can be used for distance measuring amplitude and frequency of vibrations with a vision system.

Corrélats neuronaux de la mémoire de travail en magnétoencéphalographie à l’état de repos

Purpose: There are few studies demonstrating the link between neural oscillations in magnetoencephalography (MEG) at rest and cognitive performance. Working memory is one of the most studied cognitive processes and is the ability to manipulate information on items kept in short-term memory. Heister & al. (2013) showed correlation patterns between brain oscillations at rest in MEG and performance in a working memory task (n-back). These authors showed that delta/theta activity in fronto-parietal areas is related to working memory performance. In this study, we use resting state MEG oscillations to validate these correlations with both of verbal (VWM) and spatial (SWM) working memory, and test their specificity in comparison with other cognitive abilities. Methods: We recorded resting state MEG and used clinical neuropsychological tests to assess working memory performance in 18 volunteers (6 males and 12 females). The other neuropsychological tests of the WAIS-IV were used as control tests to assess the specificity of the correlation patterns with working memory. We calculated means of Power Spectrum Density for different frequency bands (delta, 1-4Hz; theta, 4-8Hz; alpha, 8-13Hz; beta, 13-30Hz; gamma1, 30-59Hz; gamma2, 61-90Hz; gamma3, 90-120Hz; large gamma, 30-120Hz) and correlated MEG power normalised for the maximum in each frequency band at the sensor level with working memory performance. We then grouped the sensors showing a significant correlation by using a cluster algorithm. Results: We found positive correlations between both types of working memory performance and clusters in the bilateral posterior and right fronto-temporal regions for the delta band (r2 =0.73), in the fronto-middle line and right temporal regions for the theta band (r2 =0.63) as well as in the parietal regions for the alpha band (r2 =0.78). Verbal working memory and spatial working memory share a common fronto-parietal cluster of sensors but also show specific clusters. These clusters are specific to working memory, as compared to those obtained for other cognitive abilities and right posterior parietal areas, specially in slow frequencies, appear to be specific to working memory process. Conclusions: Slow frequencies (1-13Hz) but more precisely in delta/theta bands (1-8Hz), recorded at rest with magnetoencephalography, predict working memory performance and support the role of a fronto-parietal network in working memory.

The structure of line spectra,

Mode of access: Internet.

The structure of line spectra,

McGraw-Hill paperbacks.

The interferometry of reversed and non-reversed spectra.

Vol. 3 and 4 have title: Displacement interferometry by the aid of the achromatic fringes.