Sistema de detecção de intrusão em redes informáticas

Mestrado em Engenharia Electrotécnica e de Computadores

An Efficient Long Distance Echo Canceller

This paper describes an implementation of a long distance echo canceller, operating on full-duplex with hands-free and in real-time with a single Digital Signal Processor (DSP). The proposed solution is based on short length adaptive filters centered on the positions of the most significant echoes, which are tracked by time delay estimators, for which we use a new approach. To deal with double talking situations a speech detector is employed. The floating-point DSP TMS320C6713 from Texas Instruments is used with software written in C++, with compiler optimizations for fast execution. The resulting algorithm enables long distance echo cancellation with low computational requirements, suited for embbeded systems. It reaches greater echo return loss enhancement and shows faster convergence speed when compared to the conventional approach. The experimental results approach the CCITT G.165 recommendation levels.

Vertex component analysis: a fast algorithm to extract endmembers spectra from hyperspectral data

Chapter in Book Proceedings with Peer Review First Iberian Conference, IbPRIA 2003, Puerto de Andratx, Mallorca, Spain, JUne 4-6, 2003. Proceedings

Estudos de formulação de solo‐cimento e solo‐cal e respectivas aplicações

Este trabalho teve como objectivo descrever os aspectos mais relevantes, ligados ao tratamento de solos com cimento e ao melhoramento de solos com cal, com um destaque particular para a aplicação das técnicas num contexto de obras rodoviárias. Pretende‐se também, descrever a metodologia dos estudos de formulação em laboratório cujo objectivo é optimizar a percentagem de ligante hidráulico a utilizar no melhoramento ou tratamento dos solos. É também objectivo, descrever a aplicação das referidas técnicas em contexto de obra, bem como o controlo da qualidade das mesmas. Os casos práticos apresentados neste trabalho referem‐se a duas obras realizadas pela empresa Mota‐Engil, sendo que a soluçãorelacionada com o tratamento de solos com cimento foi aplicada numa obra rodoviária em regime de concessão na zona norte do país, enquanto que a solução de melhoramento de solos com cal foi aplicada numa obra aeroportuária localizada no aeroporto de Lisboa.

Aplicação para gestão de activos de rede do Aeroporto do Porto

O presente trabalho enquadra-se na área das redes de computadores, fazendo referência aos protocolos e ao conjunto de equipamentos e softwares necessários para a administração, controlo e monitorização desse tipos de infra-estruturas. Para a gestão de uma rede de dados, é essencial dispor de conhecimentos e documentação de nível técnico para representar da forma mais fiel possível a configuração da rede, seguindo passo a passo a interligação entre os equipamentos existentes e oferecendo assim uma visão o mais fidedigna possível das instalações. O protocolo SNMP é utilizado em larga escala sendo praticamente um standard para a administração de redes baseadas na tecnologia TCP/IP. Este protocolo define a comunicação entre um administrador e um agente, estabelecendo o formato e o significado das mensagens trocadas entre ambos. Tem a capacidade de suportar produtos de diferentes fabricantes, permitindo ao administrador manter uma base de dados com informações relevantes da monitorização de vários equipamentos, que pode ser consultada e analisada por softwares NMS concebidos especialmente para a gestão de redes de computadores. O trabalho apresentado nesta dissertação teve como objectivo desenvolver uma ferramenta para apoiar à gestão da infra-estrutura de comunicações do Aeroporto Francisco Sá Carneiro que permitisse conhecer em tempo real o estado dos elementos de rede, ajudar no diagnóstico de possíveis problemas e ainda apoiar a tarefa de planeamento e expansão da rede instalada. A ferramenta desenvolvida utiliza as potencialidades do protocolo SNMP para adquirir dados de monitorização de equipamentos de rede presentes na rede do AFSC, disponibilizando-os numa interface gráfica para facilitar a visualização dos parâmetros e alertas de funcionamento mais importantes na administração da rede.

Amarração de plataformas offshore flutuantes com cabos de poliéster

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Civil na Área de Especialização de Estruturas

Implementação em hardware reconfigurável de método de separação de dados hiperespetrais

Relatório do Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

Impact of urban atmospheric environment on hospital admissions in the elderly

OBJECTIVE: To analyze the impact of intra-urban atmospheric conditions on circulatory and respiratory diseases in elder adults. METHODS: Cross-sectional study based on data from 33,212 hospital admissions in adults over 60 years in the city of São Paulo, southeastern Brazil, from 2003 to 2007. The association between atmospheric variables from Congonhas airport and bioclimatic index, Physiological Equivalent Temperature, was analyzed according to the district's socioenvironmental profile. Descriptive statistical analysis and regression models were used. RESULTS: There was an increase in hospital admissions due to circulatory diseases as average and lowest temperatures decreased. The likelihood of being admitted to the hospital increased by 12% with 1ºC decrease in the bioclimatic index and with 1ºC increase in the highest temperatures in the group with lower socioenvironmental conditions. The risk of admission due to respiratory diseases increased with inadequate air quality in districts with higher socioenvironmental conditions. CONCLUSIONS: The associations between morbidity and climate variables and the comfort index varied in different groups and diseases. Lower and higher temperatures increased the risk of hospital admission in the elderly. Districts with lower socioenvironmental conditions showed greater adverse health impacts.

Job phasing aware preemption deferral

Preemptions account for a non-negligible overhead during system execution. There has been substantial amount of research on estimating the delay incurred due to the loss of working sets in the processor state (caches, registers, TLBs) and some on avoiding preemptions, or limiting the preemption cost. We present an algorithm to reduce preemptions by further delaying the start of execution of high priority tasks in fixed priority scheduling. Our approaches take advantage of the floating non-preemptive regions model and exploit the fact that, during the schedule, the relative task phasing will differ from the worst-case scenario in terms of admissible preemption deferral. Furthermore, approximations to reduce the complexity of the proposed approach are presented. Substantial set of experiments demonstrate that the approach and approximations improve over existing work, in particular for the case of high utilisation systems, where savings of up to 22% on the number of preemption are attained.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

Efficient feature selection filters for high-dimensional data

Feature selection is a central problem in machine learning and pattern recognition. On large datasets (in terms of dimension and/or number of instances), using search-based or wrapper techniques can be cornputationally prohibitive. Moreover, many filter methods based on relevance/redundancy assessment also take a prohibitively long time on high-dimensional. datasets. In this paper, we propose efficient unsupervised and supervised feature selection/ranking filters for high-dimensional datasets. These methods use low-complexity relevance and redundancy criteria, applicable to supervised, semi-supervised, and unsupervised learning, being able to act as pre-processors for computationally intensive methods to focus their attention on smaller subsets of promising features. The experimental results, with up to 10(5) features, show the time efficiency of our methods, with lower generalization error than state-of-the-art techniques, while being dramatically simpler and faster.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

Simulation of rectifier voltage malfunction on OWECS, four-level converter, HVDC light link: Smart grid context tool

This paper presents a model for the simulation of an offshore wind system having a rectifier input voltage malfunction at one phase. The offshore wind system model comprises a variable-speed wind turbine supported on a floating platform, equipped with a permanent magnet synchronous generator using full-power four-level neutral point clamped converter. The link from the offshore floating platform to the onshore electrical grid is done through a light high voltage direct current submarine cable. The drive train is modeled by a three-mass model. Considerations about the smart grid context are offered for the use of the model in such a context. The rectifier voltage malfunction domino effect is presented as a case study to show capabilities of the model. (C) 2015 Elsevier Ltd. All rights reserved.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.