957 resultados para Etching.


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An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

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This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

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The operation on how high quality single-mode operation can be readily attained on etching circles in multimode devices is discussed. Arrays of such spots can also be envisaged. Control of the polarization state is also achieved by use of deep line etches. The output filaments and beam shapes of the conventional multimode vertical cavity surface emitting lasers (VCSEL) is shown to be engineered in terms of their positions, widths, and polarizations by use of focused ion beam etching (FIBE). Several GaAs quantum well top-emitting devices with cavity diameters of 10 μm and 18 μm were investigated.

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The field emission behaviour of a series of Tetrahedrally Bonded Amorphous Carbon (ta-C) films has been measured. The films were produced using a Filtered Cathodic Vacuum Arc System. The threshold field for emission and current densities achievable have been investigated as a function of sp3/sp2 bonding ratio and nitrogen content. Typical as-grown undoped ta-C films have a threshold field of order 10-15 V/μm and optimally nitrogen-doped films exhibit fields as low as 5 V/μm. The emission as a function of back contact and front surface condition has also been considered and shows that the back contact has only a minor effect on emission efficiency. However, after etching in either an oxygen or hydrogen plasma, the films show a marked reduction in threshold field, down to as low as 2-3 V/μm, and a marked improvement in emission site density.

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We have fabricated an ultra-compact 4×4 optical matrix on InP/InGaAsP material. 1×4 MMI couplers and TIR mirrors are employed to produce a compact 1×2 mm2 device. A CH4/H2/O2 RIE dry etch process has been used to realize two-level dry etching: deep-etch for both the MMI couplers and the mirrors and shallow-etch for the rest of the routing waveguides. It was found that a metal/dielectric bilayer mask is essential for multi-dry-etch processes and high profile verticality. We have found a Ti intermediate mask for the deep-etch process which is removable by SF6 dry-etch before the following shallow process. Dry-etch removal of the intermediate mask is necessary to protect the deep-etched mirror sidewall.

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A method to fabricate polymer field-effect transistors with submicron channel lengths is described. A thin polymer film is spin coated on a prepatterned resist with a low resolution to create a thickness contrast in the overcoated polymer layer. After plasma and solvent etching, a submicron-sized line structure, which templates the contour of the prepattern, is obtained. A further lift-off process is applied to define source-drain electrodes of transistors. With a combination of ink-jet printing, transistors with channel length down to 400 nm have been fabricated by this method. We show that drive current density increases as expected, while the on/off current ratio 106 is achieved. © 2005 American Institute of Physics.

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DLC films with different thicknesses (from 100 nm to 1.9 μm) were deposited using sputtering of graphite target in pure argon atmosphere without substrate heating. Film microstructures (sp2/sp3 ratio) and mechanical properties (modulus, hardness, stress) were characterized as a function of film thickness. A thin layer of aluminum about 60 nm was deposited on the DLC film surface. Laser micromachining of Al/DLC layer was performed to form microcantilever structures, which were released using a reactive ion etching system with SF6 plasma. Due to the intrinsic stress in DLC films and bimorph Al/DLC structure, the microcantilevers bent up with different curvatures. For DLC film of 100 nm thick, the cantilever even formed microtubes. The relationship between the bimorph beam bending and DLC film properties (such as stress, modulus, etc.) were discussed in details. © 2005 Elsevier B.V. All rights reserved.

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An alternative method for seeding catalyst nanoparticles for carbon nanotubes and nanowires growth is presented. Ni nanoparticles are formed inside a 450 nm SiO2 film on (100) Si wafers through the implantation of Ni ions at fluences of 7.5×1015 and 1.7×1016 ions.cm-2 and post-annealing treatments at 700, 900 and 1100°C. After exposed to the surface by HF dip etching, the Ni nanoparticles are used as catalyst for the growth of vertically aligned carbon nanotubes by direct current plasma enhanced chemical vapor deposition. © 2007 Materials Research Society.

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This work explored the use of industrial drop-on-demand inkjet printing for masking steel surfaces on engineering components, followed by chemical etching, to produce patterned surfaces. A solvent-based ink was printed on to mild steel samples and the influences of substrate topography and substrate temperature were investigated. Contact angle measurements were used to assess wettability. Regular patterns of circular spots (∼60 /on diameter) and more complex mask patterns were printed. Variation of the substrate temperature had negligible effect on the final size of the printed drops or on the resolution achieved. Colored optical interference fringes were observed on the dried ink deposits and correlated with film thickness measurements by whitelight interferometry.

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This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

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Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.

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Surface texturing has a great potential to improve tribological performance. First, possible texturing methods were identified and classified according to their physical principles. In sequence, some alternative texturing methods are presented. Some of them are already currently used either in industry or in laboratory, and innovations or simplifications are described for them. Others are innovative techniques. Some were explored only tentatively, where basic ideas and simple experimental investigations were developed to check their validity. Others were explored in more detail, so that their practical applicability could be identified. The first texturing method was photochemical texturing using a simple and cheap apparatus. Masking with inkjet printing before chemical etching was also successful to texture metallic samples. A new method involving electrochemical texturing, without the need to previously mask the samples to be textured have been studied in terms of voltage, current, mechanical configuration of the apparatus and electrolyte flushing. Another method aims to generate randomly distributed circular pockets on steel surfaces and involves dispersion of small acid droplets in oil. The final method involves the selective formation of hard areas on a steel surface by locallised diffusion, which should then develop into a texture during wear.

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An improved technique for transferring large area graphene grown by chemical vapor deposition on copper is presented. It is based on mechanical separation of the graphene/copper by H2 bubbles during H2O electrolysis, which only takes a few tens of seconds while leaving the copper cathode intact. A semi-rigid plastic frame in combination with thin polymer layer span on graphene gives a convenient way of handling- and avoiding wrinkles and holes in graphene. Optical and electrical characterizations prove the graphene quality is better than that obtained by traditional wet etching transfer. This technique appears to be highly reproducible and cost efficient. © 2013 American Institute of Physics.

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Atom probe tomography was used to study the redistribution of platinum and arsenic atoms after Ni(Pt) silicidation of As-doped polycrystalline Si. These measurements were performed on a field-effect transistor and compared with those obtained in unpatterned region submitted to the same process. These results suggest that Pt and As redistribution during silicide formation is only marginally influenced by the confinement in microelectronic devices. On the contrary, there is a clear difference with the redistribution reported in the literature for the blanket wafers. Selective etching used to remove the non-reacted Ni(Pt) film after the first rapid heat treatment may induce this difference. © 2011 American Institute of Physics.

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The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, labon- a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1,2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3. © 2012 Journal of Visualized Experiments.