Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software for Explicitly Parallel Memory-Centric Processor Architecture

Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

Remarque sur la destruction des plantes indigènes au Brésil et sur le moyen de les en préserver / par Ladislaü Netto ; suivies d'une note sur le même sujet par M. Naudin.

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Informe de justificació de la Beca per estades per a la recerca fora de Catalunya pre-doctorals

Estudi elaborat a partir d’una estada a la Università degli Studi di Urbino, Bologna, Itàlia, entre juliol i desembre del 2005. Es revisa el concepte d’igualtat i multiculturalisme en el Mediterrani, especialment en la conca nord mediterrània com a zona de recepció de la immigració. Paral·lelament s’analitza el concepte de democràcia a la conca nord i sud mediterrània, i la relació entre aquestes dues voreres pel que fa a la percepció mateixa de democràcia i l’Estat de dret. Inclou entrevistes amb Gustavo Gozzi, Enrico Pugliese i Joseph Piqué.

Degradació en planta pilot de colorants reactius mitjançant el procés de foto-Fenton assistit amb llum solar: aplicació del procés com a pre-tractament d'un procés biològic

Estudi elaborat a partir d’una estada a la Plataforma Solar de Almería entre desembre del 2006 i gener del 2007. S’ha dut a terme la degradació en planta pilot dels colorants reactius Procion Red H-E7B i Cibacron Red FN-R mitjançant el procés de foto-Fenton aplicat com a tractament únic i com a pretractament d’un procés biològic. El procés de foto-Fenton, assistit amb llum solar, es va realitzar en un fotoreactor solar tipus Col•lector Parabòlic Compost (CPC) i el tractament biològic en un Reactor de Biomassa Immobilitzada (RBI). Com a punt de partida, i amb l’objectiu d’estudiar la reproductibilitat del sistema, es van prendre resultats obtinguts d’experiments realitzats prèviament a escala de laboratori i amb llum artificial. El paràmetre Carboni Orgànic Total (COT) es va emprar com a indicador de l’eliminació dels colorants i dels seus intermedis. En aplicar únicament el procés de foto-Fenton com a tractament, concentracions de 10 mg•l-1 de Fe (II) i 250 mg•l-1 de H2O2 per degradar 250 mg•l-1 Procion Red H-E7B, i de 20 mg•l-1 de Fe (II) i 500 mg•l-1 de H2O2 per degradar 250 mg•l-1 Cibacron Red FN-R, van reproduir els resultants obtinguts al laboratori, amb uns nivells d’eliminació de COT del 82 i 86%, respectivament. A més, l’ús beneficiós de la llum solar en el procés de foto-Fenton, juntament amb la configuració del CPC, van incrementar la velocitat de degradació respecte als resultats previs, permetent la reducció de la concentració de Fe (II) de 10 a 2 mg•l-1 (Procion Red H-E7B) i de 20 a 5 mg•l-1 (Cibacron Red FN-R) sense pèrdues d’efectivitat. D’altre banda, el sistema combinat foto-Fenton/tractament biològic en planta pilot, unes concentracions d’oxidant de 225 mg•l-1 H2O2 per Cibacron Red FN-R i 65 mg•l-1 H2O2 per Procion Red H-E7B van ser suficients per generar solucions intermèdies biodegradables i alimentar així el RBI, millorant inclús els resultats obtinguts prèviament al laboratori.

Technical innovations at the service of cheaper labour in pre-industrial Europe. The Enlightened agenda to transform the gender division of labour in silk manufacturing

In 1749, Jacques de Vaucanson patented his or tour pour tirer la soie or spindle for silk reeling. In that same year he presented his invention to the Academy of the Sciences in Paris, of which he was a member1. Jacques de Vaucanson was born in Grenoble, France, in 1709, and died in Paris in 1782. In 1741 he had been appointed inspector of silk manufactures by Louis XV. He set about reorganizing the silk industry in France, in considerable difficulty at the time due to foreign competition. Given Vaucanson’s position, his invention was intended to replace the traditional Piémontes method, and had an immediate impact upon the silk industry in France and all over Europe.

RADIC II: a fault tolerant architecture with flexible dynamic redundancy

The demand for computational power has been leading the improvement of the High Performance Computing (HPC) area, generally represented by the use of distributed systems like clusters of computers running parallel applications. In this area, fault tolerance plays an important role in order to provide high availability isolating the application from the faults effects. Performance and availability form an undissociable binomial for some kind of applications. Therefore, the fault tolerant solutions must take into consideration these two constraints when it has been designed. In this dissertation, we present a few side-effects that some fault tolerant solutions may presents when recovering a failed process. These effects may causes degradation of the system, affecting mainly the overall performance and availability. We introduce RADIC-II, a fault tolerant architecture for message passing based on RADIC (Redundant Array of Distributed Independent Fault Tolerance Controllers) architecture. RADIC-II keeps as maximum as possible the RADIC features of transparency, decentralization, flexibility and scalability, incorporating a flexible dynamic redundancy feature, allowing to mitigate or to avoid some recovery side-effects.