Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

Protection of Digital Telecom Exchanges Against Lightning Surges and Earth Faults

Low-power electronic devices used in digital telecom exchanges are vulnerable to surge voltages and currents primarily originating from natural lightning or due to the direct interactions between electric power and telecommunication lines, etc., causing the earth/ground potential rise, neutral potential rise, and faults in the system. The fault currents may flow directly to telecom lines or through the equipment to the customer's premises, causing adequate damage to the equipment and personnel safety. In wireline applications, analog or digital, central office, exchanges, and subscriber sides have to be protected. Decisive protection and protective methods have to be employed for proper functioning of the equipment under overvoltage/overcurrent conditions. Current investigation reports some interesting results obtained on the recently developed high-voltage high-current protection cards used in digital telecom exchanges. The performances of protection cards both for the ring wave and hybrid wave surges are evaluated and presented. The surge generators required for the investigation are developed and fabricated in house as per the relevant telecom standards.

CheepSync: A Time Synchronization Service for Resource Constrained Bluetooth LE Advertisers

Clock synchronization is highly desirable in distributed systems, including many applications in the Internet of Things and Humans. It improves the efficiency, modularity, and scalability of the system, and optimizes use of event triggers. For IoTH, BLE - a subset of the recent Bluetooth v4.0 stack - provides a low-power and loosely coupled mechanism for sensor data collection with ubiquitous units (e.g., smartphones and tablets) carried by humans. This fundamental design paradigm of BLE is enabled by a range of broadcast advertising modes. While its operational benefits are numerous, the lack of a common time reference in the broadcast mode of BLE has been a fundamental limitation. This article presents and describes CheepSync, a time synchronization service for BLE advertisers, especially tailored for applications requiring high time precision on resource constrained BLE platforms. Designed on top of the existing Bluetooth v4.0 standard, the CheepSync framework utilizes low-level time-stamping and comprehensive error compensation mechanisms for overcoming uncertainties in message transmission, clock drift, and other system-specific constraints. CheepSync was implemented on custom designed nRF24Cheep beacon platforms (as broadcasters) and commercial off-the-shelf Android ported smartphones (as passive listeners). We demonstrate the efficacy of CheepSync by numerous empirical evaluations in a variety of experimental setups, and show that its average (single-hop) time synchronization accuracy is in the 10 mu s range.

Optical-Phonon-Limited High-Field Transport in Layered Materials

An optical-phonon-limited velocity model has been employed to investigate high-field transport in a selection of layered 2-D materials for both, low-power logic switches with scaled supply voltages, and high-power, high-frequency transistors. Drain currents, effective electron velocities, and intrinsic cutoff frequencies as a function of carrier density have been predicted, thus providing a benchmark for the optical-phonon-limited high-field performance limits of these materials. The optical-phonon-limited carrier velocities for a selection of multi-layers of transition metal dichalcogenides and black phosphorus are found to be modest compared to their n-channel silicon counterparts, questioning the utility of biasing these devices in the source-injection dominated regime. h-BN, at the other end of the spectrum, is shown to be a very promising material for high-frequency, high-power devices, subject to the experimental realization of high carrier densities, primarily due to its large optical-phonon energy. Experimentally extracted saturation velocities from few-layer MoS2 devices show reasonable qualitative and quantitative agreement with the predicted values. The temperature dependence of the measured v(sat) is discussed and compared with the theoretically predicted dependence over a range of temperatures.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.