739 resultados para VOLTAGES
Resumo:
Three-terminal ballistic junctions (TBJs) are fabricated from a high-mobility InP/In0.75Ga0.25As heterostructure by electron-beam lithography. The voltage output from the central branch is measured as a function of the voltages applied to the left and right branches of the TBJs. The measurements show that the TBJs possess an intrinsic nonlinearity. Based on this nonlinearity, a novel room-temperature functional frequency mixer and phase detector are realized. The TBJ frequency mixer and phase detector are expected to have advantages over traditional circuits in terms of simple structure, small size and high speed, and can be used as a new type of building block in nanoelectronics.
Resumo:
In this work a practical scheme is developed for the first-principles study of time-dependent quantum transport. The basic idea is to combine the transport master equation with the well-known time-dependent density functional theory. The key ingredients of this paper include (i) the partitioning-free initial condition and the consideration of the time-dependent bias voltages which base our treatment on the Runge-Gross existence theorem; (ii) the non-Markovian master equation for the reduced (many-body) central system (i.e., the device); and (iii) the construction of Kohn-Sham master equations for the reduced single-particle density matrix, where a number of auxiliary functions are introduced and their equations of motion (EOMs) are established based on the technique of spectral decomposition. As a result, starting with a well-defined initial state, the time-dependent transport current can be calculated simultaneously along with the propagation of the Kohn-Sham master equation and the EOMs of the auxiliary functions.
Resumo:
Complex Fourier transformation (CFT) has been employed to analyse contactless electroreflectance (CER) spectra from an undoped-n(+) GaAs structure with various ac modulations and dc bias voltages. The CFT spectra of CER have been compared with those of photoreflectance (PR). It has been found that the CER non-flat modulation is between the built-in electric field and a larger electric field which increases with the modulation voltage. The result has been explained by the screening of the applied modulation electric field in one of the two half modulation cycles and the trapping of electrons in surface states in the other half modulation cycle. The dc bias does not change the CER spectra, hence their CFT spectra. This is because of the screening of the applied dc bias electric field.
Resumo:
The techniques of fabricating metallic air bridges using different resists in a one-step electron beam lithography are presented. The exposure process employed a single-layer polymethyl methacrylate (PMMA) or photoresists with either different doses in the span and feet areas or with varying acceleration voltage of the electron beam. The process using photoresists with different doses has produced air bridges more stable than what the PMMA method using various acceleration voltages would achieve. Using this method, air bridges up to 12 mu m long have been fabricated. The length and height of these metallic air bridges vary with the photoresist thickness. (c) 2006 American Institute of Physics.
Resumo:
AMPS simulator, which was developed by Pennsylvania State University, has been used to simulate photovoltaic performances of nc-Si:H/c-Si solar cells. It is shown that interface states are essential factors prominently influencing open circuit voltages (V-OC) and fill factors (FF) of these structured solar cells. Short circuit current density (J(SC)) or spectral response seems more sensitive to the thickness of intrinsic a-Si:H buffer layers inserted into n(+)-nc-Si:H layer and p-c-Si substrates. Impacts of bandgap offset on solar cell performances have also been analyzed. As DeltaE(C) increases, degradation of VOC and FF owing to interface states are dramatically recovered. This implies that the interface state cannot merely be regarded as carrier recombination centres, and impacts of interfacial layer on devices need further investigation. Theoretical maximum efficiency of up to 31.17% (AM1.5,100mW/cm(2), 0.40-1.1mum) has been obtained with BSF structure, idealized light-trapping effect(R-F=0, R-B=1) and no interface states.
Resumo:
Phosphor-doped nano-crystalline silicon ((n))nc-Si:H) films are successfully grown on the p-type (100) oriented crystal silicon ((p) c-Si) substrate by conventional plasma-enhanced chemical vapor deposition method. The films are obtained using high H-2 diluted SiH4 as a reaction gas source and using PH3 as the doping gas source of phosphor atoms. Futhermore, the heterojunction diodes are also fabricated by using (n)nc-Si:H films and (p)c-Si substrate. I-V properties are investigated in the temperature range of 230-420K. The experimental results domenstrate that (n)nc-Si:H/(p) c-Si heterojunction is a typical abrupt heterojunction having good rectifing and temperature properties. Carrier transport mechanisms are tunneling - recombination model at forward bias voltages. In the range of low bias voltages ( V-F< 0.8 V), the current is determined by recombination at the (n)nc-Si:H side of the space charge region, while the current becomes tunneing at higher bias voltages( V-F>1.0 V). The present heterojunction has high reverse breakdown voltage ( > - 75 V) and low reverse current (approximate to nA).
Resumo:
An three phase adjustable output voltage rectifier with constant power flow based on waveform gap patching principle is resented. By patching the gapes in the phase currents in parallel way as well as the ripple of the output voltage in series way, it implements the constant power flow from the three-phase line to the DC output without using any line frequency (and its harmonics) energy storage components. Principally, by treating only 22.4% power of the needed power output, this rectifier can supply constant power flow with adjustable output voltages without bring about any harmonic interferences to the power utility and achieve unite power factor.
Resumo:
This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.
Resumo:
The output characteristics of micro-solar cell arrays are analyzed on the basis of a modified model in which the shunt resistance between cell lines results in current leakage. The modification mainly consists of adding a shunt resistor network to the traditional model. The obtained results agree well with the reported experimental results. The calculation results demonstrate that leakage current in substrate affects seriously the performance of GaAs micro- solar cell arrays. The performance of arrays can be improved by reducing the number of cells per line. In addition, at a certain level of integration, an appropriate space occupancy rate of the single cell is recommended for ensuring high open circuit voltages, and it is more appropriate to set the rates at 80%-90% through the calculation.
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Charge build-up process in the emitter of a double-barrier resonant tunneling structure is studied by using photoluminescence spectroscopy. Clear evidence is obtained that the charge accumulation in the emitter keeps almost constant with bias voltages in the resonant regime, while it increases remarkably with bias voltages beyond resonant regime. The optical results are in good agreement with the electrical measurement. It is demonstrated that the band gap renormalization plays a certain rob in the experiment.
Resumo:
The sidegating effect on the Schottky barrier in ion-implanted GaAs was investigated with capacitance-voltage profiling at various negative substrate voltages. It was demonstrated that the negative substrate voltage modulates the Schottky depletion region width as well as the space charge region at the substrate-active channel interface. (C) 1995 American Institute of Physics.
Resumo:
This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator (SO1) technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic "1" while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable "read" operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin (SNM) of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
Resumo:
A realistic measurement setup for a system such system measured by a mesoscopie detector,is theoretically as a charged two-state (qubit) or multi-state quantum studied. To properly describe the measurement-induced back-action,a detailed-balance preserved quantum master equation treatment is developed. The established framework is applicable for arbitrary voltages and temperatures.
Resumo:
To improve the sensitivity of our laser radar system, we provided a set of control method for APDs (Avalanched Photodiodes) based on single-chip computer together with the circuits dealing with noise and temperature. It adjusts the voltages intelligently and maintains the APD's optimal working status.
Resumo:
A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.