Estimated lifetimes of road pavements in Sweden using time-to-event analysis

Maintenance planning of road pavement requires reliable estimates of roads’ lifetimes. In determining the lifetime of a road, this study combines maintenance activities and road condition measurements. The scope of the paper is to estimate lifetimes of road pavements in Sweden with time to event analysis. The model used includes effects of pavement type, road type, bearing capacity, road width, speed limit, stone size and climate zone, where the model is stratified according to traffic load. Among the nine analyzed pavement types, stone mastic had the longest expected lifetime, 32 percent longer than asphalt concrete. Among road types, ordinary roads with cable barriers had 30 percent shorter lifetime than ordinary roads. Increased speed lowered the lifetime, while increased stone size (up to 20 mm) and increased road width lengthened the lifetime. The results are of importance for life cycle cost analysis and road management.

PrIMe: A Methodology for Developing Provenance-Aware Applications

Provenance refers to the past processes that brought about a given (version of an) object, item or entity. By knowing the provenance of data, users can often better understand, trust, reproduce, and validate it. A provenance-aware application has the functionality to answer questions regarding the provenance of the data it produces, by using documentation of past processes. PrIMe is a software engineering technique for adapting application designs to enable them to interact with a provenance middleware layer, thereby making them provenance-aware. In this article, we specify the steps involved in applying PrIMe, analyse its effectiveness, and illustrate its use with two case studies, in bioinformatics and medicine.

Food Line at a New York Trade School Social Event

This black and white photograph shows a large group of men lining up for dessert at a New York Trade School social event.

Speaker at a New York Trade School Social Event

A speaker is pictured along with other important guests on the dais at a New York Trade School social event. Black and white photograph.

Guests at a New York Trade School Social Event

This photograph features a table of guests at a New York Trade School social event. Photograph is black and white.

Charles W. Merideth at City Tech event

Charles W. Merideth is shown looking at pictures in a group at an event in the Atrium Building at City Tech. Charles W. Merideth was the sixth president of the City Tech. He was formerly installed on October 19, 1990. Before coming to City Tech, Merideth had a long career in science and higher education. Under Merideth, the College expanded the number of baccalaureate programs offered by the College.

Charles W. Merideth at a Multi-Cultural Week Event

Charles W. Merideth is pictured at the "Asia at a Glance"exhibit. The exhibit was a part of the May 1991 Multi-Cultural Week at City Tech. Charles W. Merideth was the sixth president of the City Tech. He was formerly installed on October 19, 1990. Before coming to City Tech, Merideth had a long career in science and higher education. Under Merideth, the College expanded the number of baccalaureate programs offered by the College.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.