338 resultados para HDFS bottleneck


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The objective of the PhD thesis was to research technologies and strategies to reduce fuel consumption and pollutants emission produced by internal combustion engines. In order to meet this objective my activity was focused on the research of advanced controls based on cylinder pressure feedback. These types of control strategies were studied because they present promising results in terms of engine efficiency enhancement. In the PhD dissertation two study cases are presented. The first case is relative to a control strategy to be used at the test bench for the optimisation of the spark advance calibration of motorcycle Engine. The second case is relative to a control strategy to be used directly on board of mining engines with the objective or reducing the engine consumption and correct ageing effects. In both cases the strategies proved to be effective but their implementation required the use of specific toolchains for the measure of the cylinder pressure feedback that for a matter of cost makes feasible the strategy use only for applications: • At test bench • In small-markets like large off-road engines The major bottleneck that prevents the implementation of these strategies on mass production is the cost of cylinder pressure sensor. In order to tackle this issue, during the PhD research, the development of a low-cost sensor for the estimation of cylinder pressure was studied. The prototype was a piezo-electric washer designed to replace the standard spark-plug washer or high-pressure fuel injectors gasket. From the data analysis emerged the possibility to use the piezo-electric prototype signal to evaluate with accuracy several combustion metrics compatible for the implementation of advanced control strategies in on-board applications. Overall, the research shows that advanced combustion controls are feasible and beneficial, not only at the test bench or on stationary engines, but also in mass-produced engines.

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High Energy efficiency and high performance are the key regiments for Internet of Things (IoT) end-nodes. Exploiting cluster of multiple programmable processors has recently emerged as a suitable solution to address this challenge. However, one of the main bottlenecks for multi-core architectures is the instruction cache. While private caches fall into data replication and wasting area, fully shared caches lack scalability and form a bottleneck for the operating frequency. Hence we propose a hybrid solution where a larger shared cache (L1.5) is shared by multiple cores connected through a low-latency interconnect to small private caches (L1). However, it is still limited by large capacity miss with a small L1. Thus, we propose a sequential prefetch from L1 to L1.5 to improve the performance with little area overhead. Moreover, to cut the critical path for better timing, we optimized the core instruction fetch stage with non-blocking transfer by adopting a 4 x 32-bit ring buffer FIFO and adding a pipeline for the conditional branch. We present a detailed comparison of different instruction cache architectures' performance and energy efficiency recently proposed for Parallel Ultra-Low-Power clusters. On average, when executing a set of real-life IoT applications, our two-level cache improves the performance by up to 20% and loses 7% energy efficiency with respect to the private cache. Compared to a shared cache system, it improves performance by up to 17% and keeps the same energy efficiency. In the end, up to 20% timing (maximum frequency) improvement and software control enable the two-level instruction cache with prefetch adapt to various battery-powered usage cases to balance high performance and energy efficiency.

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Embedding intelligence in extreme edge devices allows distilling raw data acquired from sensors into actionable information, directly on IoT end-nodes. This computing paradigm, in which end-nodes no longer depend entirely on the Cloud, offers undeniable benefits, driving a large research area (TinyML) to deploy leading Machine Learning (ML) algorithms on micro-controller class of devices. To fit the limited memory storage capability of these tiny platforms, full-precision Deep Neural Networks (DNNs) are compressed by representing their data down to byte and sub-byte formats, in the integer domain. However, the current generation of micro-controller systems can barely cope with the computing requirements of QNNs. This thesis tackles the challenge from many perspectives, presenting solutions both at software and hardware levels, exploiting parallelism, heterogeneity and software programmability to guarantee high flexibility and high energy-performance proportionality. The first contribution, PULP-NN, is an optimized software computing library for QNN inference on parallel ultra-low-power (PULP) clusters of RISC-V processors, showing one order of magnitude improvements in performance and energy efficiency, compared to current State-of-the-Art (SoA) STM32 micro-controller systems (MCUs) based on ARM Cortex-M cores. The second contribution is XpulpNN, a set of RISC-V domain specific instruction set architecture (ISA) extensions to deal with sub-byte integer arithmetic computation. The solution, including the ISA extensions and the micro-architecture to support them, achieves energy efficiency comparable with dedicated DNN accelerators and surpasses the efficiency of SoA ARM Cortex-M based MCUs, such as the low-end STM32M4 and the high-end STM32H7 devices, by up to three orders of magnitude. To overcome the Von Neumann bottleneck while guaranteeing the highest flexibility, the final contribution integrates an Analog In-Memory Computing accelerator into the PULP cluster, creating a fully programmable heterogeneous fabric that demonstrates end-to-end inference capabilities of SoA MobileNetV2 models, showing two orders of magnitude performance improvements over current SoA analog/digital solutions.

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The climate crisis is the greatest challenge humanity has ever faced, and in 2023 the average global temperature reached new records, prompting the UN Secretary General to declare that 'the era of global warming is over, and the era of global boiling has arrived'. In this context, urban areas play a key role, and can be considered a bottleneck of the climate crisis. The European Commission is investing billions of euros in research and innovation projects in urban areas, while the European Green Deal strategy has the ambition of making Europe the first carbon-neutral continent on the planet by 2050. However, studies and research show that the causes of the climate crisis are rooted in an economic system that produces profound inequalities, and the very solutions to address the consequences of global warming risk deepening them. In this context, the role of cities is not only to decarbonise their urban fabric, but to build solutions to the social challenge posed by the climate crisis, promoting paradigm shifts capable of producing trajectories towards so-called 'climate justice'. This research analyses, through a holistic view, European policies in these fields, and delves into the actions and projects of four European cities - Amsterdam, Bilbao, Freiburg, and Lisbon - through a qualitative approach aimed at identifying strengths and contradictions of strategies to tackle the climate crisis. Delving into the collective dynamics and social impacts of the actions promoted, the research proposes a comprehensive view of the role that urban areas can play not only in decarbonising society, but in promoting a paradigm shift capable of addressing the economic causes and social consequences of the climate crisis.

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In the Massive IoT vision, millions of devices need to be connected to the Internet through a wireless access technology. However, current IoT-focused standards are not fully prepared for this future. In this thesis, a novel approach to Non-Orthogonal techniques for Random Access, which is the main bottleneck in high density systems, is proposed. First, the most popular wireless access standards are presented, with a focus on Narrowband-IoT. Then, the Random Access procedure as implemented in NB-IoT is analyzed. The Non-Orthogonal Random Access technique is presented next, along with two potential algorithms for the detection of non-orthogonal preambles. Finally, the performance of the proposed solutions are obtained through numerical simulations.

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The decomposition of Feynman integrals into a basis of independent master integrals is an essential ingredient of high-precision theoretical predictions, that often represents a major bottleneck when processes with a high number of loops and legs are involved. In this thesis we present a new algorithm for the decomposition of Feynman integrals into master integrals with the formalism of intersection theory. Intersection theory is a novel approach that allows to decompose Feynman integrals into master integrals via projections, based on a scalar product between Feynman integrals called intersection number. We propose a new purely rational algorithm for the calculation of intersection numbers of differential $n-$forms that avoids the presence of algebraic extensions. We show how expansions around non-rational poles, which are a bottleneck of existing algorithms for intersection numbers, can be avoided by performing an expansion in series around a rational polynomial irreducible over $\mathbb{Q}$, that we refer to as $p(z)-$adic expansion. The algorithm we developed has been implemented and tested on several diagrams, both at one and two loops.

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Nel mondo dell’industria, la produzione senza sprechi costituisce fonte di vantaggio competitivo. Per questo, molte aziende cercano di efficientare i propri processi attraverso gli strumenti della Lean Manufacturing. L’obiettivo di questa tesi è proprio quello di trovare una soluzione per la minimizzazione degli sprechi all’interno del contesto aziendale in cui sono stato inserito come tirocinante. In primis, si cercherà di descrivere in modo dettagliato l’azienda pressa la quale si è svolta l’attività di tirocinio. Successivamente verrà illustrato lo stato AS-IS dell’azienda insieme alle problematiche che sta fronteggiando in questo momento. Dopo la descrizione del problema all’interno del contesto aziendale, si analizzeranno i dati presi direttamente sul campo di lavoro. A seguire, dopo l’approvazione da parte del top management della soluzione migliorativa trovata, avverrà la descrizione dello stato TO-BE. In conclusione, verranno messi a confronto i dati dello stato AS-IS con quelli del TO-BE per costruire il dato aggregato dell’attività svolta in azienda. Questo riassume brevemente il lavoro di tesi svolto in azienda, che ha permesso di ridurre di qualche punto percentuale i fermi macchina e di efficientare il sistema produttivo.

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The recording and processing of voice data raises increasing privacy concerns for users and service providers. One way to address these issues is to move processing on the edge device closer to the recording so that potentially identifiable information is not transmitted over the internet. However, this is often not possible due to hardware limitations. An interesting alternative is the development of voice anonymization techniques that remove individual speakers characteristics while preserving linguistic and acoustic information in the data. In this work, a state-of-the-art approach to sequence-to-sequence speech conversion, ini- tially based on x-vectors and bottleneck features for automatic speech recognition, is explored to disentangle the two acoustic information using different pre-trained speech and speakers representation. Furthermore, different strategies for selecting target speech representations are analyzed. Results on public datasets in terms of equal error rate and word error rate show that good privacy is achieved with limited impact on converted speech quality relative to the original method.