972 resultados para voltage stability margin
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The Container Loading Problem (CLP) literature has traditionally evaluated the dynamic stability of cargo by applying two metrics to box arrangements: the mean number of boxes supporting the items excluding those placed directly on the floor (M1) and the percentage of boxes with insufficient lateral support (M2). However, these metrics, that aim to be proxies for cargo stability during transportation, fail to translate real-world cargo conditions of dynamic stability. In this paper two new performance indicators are proposed to evaluate the dynamic stability of cargo arrangements: the number of fallen boxes (NFB) and the number of boxes within the Damage Boundary Curve fragility test (NB_DBC). Using 1500 solutions for well-known problem instances found in the literature, these new performance indicators are evaluated using a physics simulation tool (StableCargo), replacing the real-world transportation by a truck with a simulation of the dynamic behaviour of container loading arrangements. Two new dynamic stability metrics that can be integrated within any container loading algorithm are also proposed. The metrics are analytical models of the proposed stability performance indicators, computed by multiple linear regression. Pearson’s r correlation coefficient was used as an evaluation parameter for the performance of the models. The extensive computational results show that the proposed metrics are better proxies for dynamic stability in the CLP than the previous widely used metrics.
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Dissertation to obtain a Master Degree in Biotechnology
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Dissertation presented to obtain the PhD degree in Biochemistry
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21st Annual Conference of the International Group for Lean Construction – IGLC 21 – Fortaleza, Brazil
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Dissertation presented to obtain the Ph.D degree in Biochemistry
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Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e de Computadores, pela Universidade Nova de Ciências e Tecnologia
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Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores
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Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores
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The GxE interaction only became widely discussed from evolutionary studies and evaluations of the causes of behavioral changes of species cultivated in environments. In the last 60 years, several methodologies for the study of adaptability and stability of genotypes in multiple environments trials were developed in order to assist the breeder's choice regarding which genotypes are more stable and which are the most suitable for the crops in the most diverse environments. The methods that use linear regression analysis were the first to be used in a general way by breeders, followed by multivariate analysis methods and mixed models. The need to identify the genetic and environmental causes that are behind the GxE interaction led to the development of new models that include the use of covariates and which can also include both multivariate methods and mixed modeling. However, further studies are needed to identify the causes of GxE interaction as well as for the more accurate measurement of its effects on phenotypic expression of varieties in competition trials carried out in genetic breeding programs.
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In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology.
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Quadrature oscillators are key elements in modern radio frequency (RF) transceivers and very useful nowadays in wireless communications, since they can provide: low quadrature error, low phase-noise, and wide tuning range (useful to cover several bands). RC oscillators can be fully integrated without the need of external components (external high Q-inductors), optimizing area, cost, and power consumption. The conventional structure of ring oscillator offers poor frequency stability and phasenoise, low quality factor (Q), and besides being vulnerable to process, voltage and temperature (PVT) variations, its performance degrades as the frequency of operation increases. This thesis is devoted to quadrature oscillators and presents a detailed comparative study of ring oscillator and shift register (SR) approaches. It is shown that in SRs both phase-noise and phase error are reduced, while ring oscillators have the advantage of occupying less area and less consumption due to the reduced number of components in the circuit. Thus, although ring oscillators are more suitable for biomedical applications, SRs are more appropriate for wireless applications, especially when specification requirements are more stringent and demanding. The first architecture studied consists in a simple CMOS ring oscillator employing an odd number of static single-ended inverters as delay cells. Subsequently, the quadrature 4-stage ring oscillator concept is shown and post-layout simulations are presented. The 3 and 4-phase single-frequency local oscillator (LO) generators employing SRs are presented, the latter with 50% and 25% duty-cycles. The circuits operate at 600 MHz and 900 MHz, and were designed in a 130 nm standard CMOS technology with a voltage supply of 1.2 V.
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The thrust towards energy conservation and reduced environmental footprint has fueled intensive research for alternative low cost sources of renewable energy. Organic photovoltaic cells (OPVs), with their low fabrication costs, easy processing and flexibility, represent a possible viable alternative. Perylene diimides (PDIs) are promising electron-acceptor candidates for bulk heterojunction (BHJ) OPVs, as they combine higher absorption and stability with tunable material properties, such as solubility and position of the lowest unoccupied molecular orbital (LUMO) level. A prerequisite for trap free electron transport is for the LUMO to be located at a level deeper than 3.7 eV since electron trapping in organic semiconductors is universal and dominated by a trap level located at 3.6 eV. Although the mostly used fullerene acceptors in polymer:fullerene solar cells feature trap-free electron transport, low optical absorption of fullerene derivatives limits maximum attainable efficiency. In this thesis, we try to get a better understanding of the electronic properties of PDIs, with a focus on charge carrier transport characteristics and the effect of different processing conditions such as annealing temperature and top contact (cathode) material. We report on a commercially available PDI and three PDI derivatives as acceptor materials, and its blends with MEH-PPV (Poly[2-methoxy 5-(2-ethylhexyloxy)-1,4-phenylenevinylene]) and P3HT (Poly(3-hexylthiophene-2,5-diyl)) donor materials in single carrier devices (electron-only and hole-only) and in solar cells. Space-charge limited current measurements and modelling of temperature dependent J-V characteristics confirmed that the electron transport is essentially trap-free in such materials. Different blend ratios of P3HT:PDI-1 (1:1) and (1:3) show increase in the device performance with increasing PDI-1 ratio. Furthermore, thermal annealing of the devices have a significant effect in the solar cells that decreases open-circuit voltage (Voc) and fill factor FF, but increases short-circuit current (Jsc) and overall device performance. Morphological studies show that over-aggregation in traditional donor:PDI blend systems is still a big problem, which hinders charge carrier transport and performance in solar cells.
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This paper presents a comprehensive comparison of a current-source converter and a voltage-source converter for three-phase electric vehicle (EV) fast battery chargers. Taking into account that the current-source converter (CSC) is a natural buck-type converter, the output voltage can assume a wide range of values, which varies between zero and the maximum instantaneous value of the power grid phase-to-phase voltage. On the other hand, taking into account that the voltage-source converter (VSC) is a natural boost-type converter, the output voltage is always greater than the maximum instantaneous value of the power grid phase-to-phase voltage, and consequently, it is necessary to use a dc-dc buck-type converter for applications as EV fast battery chargers. Along the paper is described in detail the principle of operation of both the CSC and the VSC for EV fast chargers, as well as the main equations of the power theory and current control strategies. The comparison between both converters is mainly established in terms of the total harmonic distortion of the grid current and the estimated efficiency for a range of operation between 10 kW and 50 kW.