Dependência estrutural da capacidade de rotação plástic em vigas de concreto armado

Summary In this work the structural dependence of plastic rotation capacity in RC beams is evaluated using the Finite Element Method. The objective is to achieve a better understanding of the non-linear behavior of reinforced concrete members and perform extensive parameter studies, using a rational model developed by Bigaj [1] to analyze the phenomenon of plastic rotation capacity in reinforced concrete members. It is assumed that only bending failure is relevant due to sufficient member resistance against shear and torsion. The paper begins with the physical and theoretical background of the phenomenon of plastic hinge development in RC structures. Special emphasis is laid on the issue of structural dependence of deformation capacity of plastic hinges in RC members. Member size dependence and influence of properties of construction materials were emphasized as well. The essential components of the Bigajs model for calculating the plastic rotation capacity are discussed. The behaviour of the plastic hinge is analysed taking into account the strain localisation in the damage zones of the hinge region. The Fictitious Crack Model (FCM) and the Compressive Damage Zone Model (CDZ) are adopted in a Fracture Mechanics approach to model the behaviour of concrete in tension and compression, respectively. The approach is implemented in FEMOOP, a FEM in-house solver under development, and applied to evaluate ductility in 2D beams. The models were generated with GiD, a pre-processor and post-processor developed by CIMNE, and analyzed with the capabilities implemented in FEMOOP. © Universitat Politècnica de Catalunya, Barcelona, España 2010.

LUTS: A lightweight user-level transaction scheduler

Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios. © 2011 Springer-Verlag.

HW/SW for an intelligent transducer network based on IEEE 1451 standard

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation. © 2011 Elsevier B.V.

NCAP embedded using structured programming

This paper presents a network node embedded based on IEEE 1451 standard developed using structured programming to access the transducers in the WTIM. The NCAP was developed using Nios II processor and uClinux, a embedded operating system developed to features restricted hardware. Both hardware and software have dynamics features and they can be configured based in the application features. Based in this features, the NCAP was developed using the minimum components of hardware and software to that being implemented in remote environment like central point of data request. Many NCAP works are implemented with an object oriented structure. This is different from the surrounding implementations. In this project the NCAP was developed using structured programming. The tests of the NCAP were made using a ZigBee interface between NCAP and WTIM and the system demonstrated in areas of difficult access for long period of time due to need for low power consumption. © 2012 IEEE.

Energy-performance tradeoffs in software transactional memory

Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.

Transaction scheduling using dynamic conflict avoidance

Software transaction memory (STM) systems have been used as an approach to improve performance, by allowing the concurrent execution of atomic blocks. However, under high-contention workloads, STM-based systems can considerably degrade performance, as transaction conflict rate increases. Contention management policies have been used as a way to select which transaction to abort when a conflict occurs. In general, contention managers are not capable of avoiding conflicts, as they can only select which transaction to abort and the moment it should restart. Since contention managers act only after a conflict is detected, it becomes harder to effectively increase transaction throughput. More proactive approaches have emerged, aiming at predicting when a transaction is likely to abort, postponing its execution. Nevertheless, most of the proposed proactive techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction to run. This article proposes LUTS, a lightweight user-level transaction scheduler. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. We discuss LUTS design and propose a dynamic conflict-avoidance heuristic built around its scheduling capabilities. Experimental results, conducted with the STAMP and STMBench7 benchmark suites, running on TinySTM and SwissTM, show how our conflict-avoidance heuristic can effectively improve STM performance on high contention applications. © 2012 Springer Science+Business Media, LLC.

Estruturação do conhecimento e relações semânticas: uma ontologia para o domínio da naonociência e nanotecnologia

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Avaliação e implementação de métodos de estimação de tempo de atraso de sinais de ultra-som

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Controle da posição da perna de pessoas hígidas utilizando um controlador PID

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Algoritmos de detecção de bordas implementados em FPGA

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Demodulação de sinais interferométricos de saída de sensor eletro-óptico de tensões elevadas utilizando processador digital de sinais

Pós-graduação em Engenharia Elétrica - FEIS

Implementação de um controle digital para o compensador regenerativo de potência ativa

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Desenvolvimento de sistema de aquisição e processamento para aplicações em qualidade de energia

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Um novo sistema de refrigeração com controle de temperatura, compressor aberto, máquina de indução trifásica com velocidade variável e correção ativa do fator de potência do estágio de entrada

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Pré-regulador retificador boost com controle digital por valores médios, para sistema de iluminação fluorescente multi-lâmpadas, utilizando dispositivo FPGA e VHDL

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)