998 resultados para Reference Architecture


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Background: Hypertension is a public health problem, considering its high prevalence, low control rate and cardiovascular complications. Objective: Evaluate the control of blood pressure (BP) and cardiovascular outcomes in patients enrolled at the Reference Center for Hypertension and Diabetes, located in a medium-sized city in the Midwest Region of Brazil. Methods: Population-based study comparing patients enrolled in the service at the time of their admission and after an average follow-up of five years. Participants were aged ≥18 years and were regularly monitored at the Center up to 6 months before data collection. We assessed demographic variables, BP, body mass index, risk factors, and cardiovascular outcomes. Results: We studied 1,298 individuals, predominantly women (60.9%), and with mean age of 56.7±13.1 years. Over time, there was a significant increase in physical inactivity, alcohol consumption, diabetes, dyslipidemia, and excessive weight. As for cardiovascular outcomes, we observed an increase in stroke and myocardial revascularization, and a lower frequency of chronic renal failure. During follow-up, there was significant improvement in the rate of BP control (from 29.6% to 39.6%; p = 0.001) and 72 deaths, 91.7% of which were due to cardiovascular diseases. Conclusion: Despite considerable improvements in the rate of BP control during follow-up, risk factors worsened and cardiovascular outcomes increased.

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Background: Physiological reflexes modulated primarily by the vagus nerve allow the heart to decelerate and accelerate rapidly after a deep inspiration followed by rapid movement of the limbs. This is the physiological and pharmacologically validated basis for the 4-s exercise test (4sET) used to assess the vagal modulation of cardiac chronotropism. Objective: To present reference data for 4sET in healthy adults. Methods: After applying strict clinical inclusion/exclusion criteria, 1,605 healthy adults (61% men) aged between 18 and 81 years subjected to 4sET were evaluated between 1994 and 2014. Using 4sET, the cardiac vagal index (CVI) was obtained by calculating the ratio between the duration of two RR intervals in the electrocardiogram: 1) after a 4-s rapid and deep breath and immediately before pedaling and 2) at the end of a rapid and resistance-free 4-s pedaling exercise. Results: CVI varied inversely with age (r = -0.33, p < 0.01), and the intercepts and slopes of the linear regressions between CVI and age were similar for men and women (p > 0.05). Considering the heteroscedasticity and the asymmetry of the distribution of the CVI values according to age, we chose to express the reference values in percentiles for eight age groups (years): 18–30, 31–40, 41–45, 46–50, 51–55, 56–60, 61–65, and 66+, obtaining progressively lower median CVI values ranging from 1.63 to 1.24. Conclusion: The availability of CVI percentiles for different age groups should promote the clinical use of 4sET, which is a simple and safe procedure for the evaluation of vagal modulation of cardiac chronotropism.

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Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

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The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

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Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.