Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.

GPU-accelerated optimization of fuel treatments for mitigating wildfire hazard

Fuel treatment is considered a suitable way to mitigate the hazard related to potential wildfires on a landscape. However, designing an optimal spatial layout of treatment units represents a difficult optimization problem. In fact, budget constraints, the probabilistic nature of fire spread and interactions among the different area units composing the whole treatment, give rise to challenging search spaces on typical landscapes. In this paper we formulate such optimization problem with the objective of minimizing the extension of land characterized by high fire hazard. Then, we propose a computational approach that leads to a spatially-optimized treatment layout exploiting Tabu Search and General-Purpose computing on Graphics Processing Units (GPGPU). Using an application example, we also show that the proposed methodology can provide high-quality design solutions in low computing time. © 2013 The Authors. Published by Elsevier B.V.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.

The next-generation sequencing technology: A technology review and future perspective

As one of the most powerful tools in biomedical research, DNA sequencing not only has been improving its productivity in an exponential growth rate but also been evolving into a new layout of technological territories toward engineering and physical disciplines over the past three decades. In this technical review, we look into technical characteristics of the next-gen sequencers and provide prospective insights into their future development and applications. We envisage that some of the emerging platforms are capable of supporting the $1000 genome and $100 genome goals if given a few years for technical maturation. We also suggest that scientists from China should play an active role in this campaign that will have profound impact on both scientific research and societal healthcare systems.

Influence of heated catalyzer on thermal distribution of substrate in HWCVD system

Based on Stefan-Boltzman and Lambert theorems, the radiation energy distribution on substrate (REDS) from catalyzer with parallel filament geometry has been simulated by variation of filament and system layout in hot-wire chemical vapor deposition. The REDS uniformity is sensitive to the distance between filament and substrate d(f-s) when d(f-s) less than or equal to 4 cm. As d(f-s) > 4 cm, the REDS uniformity is independent of d(f-s) and is mainly determined by filament number and filament separation. Two-dimensional calculation shows that the REDS uniformity is limited by temperature decay at filament edges. The simulation data are in good agreement with experiments. (C) 2003 Elsevier Science B.V. All rights reserved.

A Low Power Baseband Chain for CMMB Application

This paper presents experimental results of an analog baseband circuit for China Multimedia Mobile Broadcasting (CMMB) direct conversion receiver in 0.35um SiGe BiCMOS process. It is the first baseband of CMMB RFIC reported so far. A 8(th)-order chebyshev low pass filter (LPF) with calibration system is used in the analog baseband circuit, the filter provides 0.5 dB passband ripple and -35 dB attenuation at 6MHz with the cutoff frequency at 4MHz, the calibration of filter is reported to achieve the bandwidth accuracy of 3%. The baseband variable gain amplifier (VGA) achieves more than 40 dB gain tuning with temperature compensation. In addition, A DC offset cancellation circuit is also introduced to remove the offset from layout and self-mixing, and the remaining offset voltage and current consumption are only 6mV and 412uA respectively. Implemented in a 0.35um SiGe technology with 1.1 mm(2) die size, this tuner baseband achieves OIP3 of 25.5 dBm and dissipate 16.4 mA under 2.8-V supply.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

基于约束语义的双手交互场景布局系统

以家居布局为应用背景,采用双手交互的分工协作,结合2种不同维度的输入设备的特性改进3D地图技术和遥取技术,实现地图和场景的无缝融合以及远处物体的直接操作;增添场景约束语义,实现物体的成组移动.通过语义识别和反馈来实现场景布局的精确定位.

在ICU中实现少数民族文字的处理

基于ISO/ IEC 10646和UNICODE国际标准,用传统的字体技术(如TrueType)来实现少数民族文字处理所面临的一个"瓶颈"问题是:"变形显现字符"不存在确定的码位.这也是多年来民文系统重复开发、互不兼容的根本原因.本文基于ICU的文字处理体系结构,阐述了完全支持Unicode标准的少数民族文字(本文主要指蒙古文字、维文、藏文等)的实现方法.文中首先介绍了少数民族文字的特点,分析其与拉丁文字、汉字在计算机输入、输出过程中的不同之处,并指出少数民族文字处理的难点.其次介绍了一种能满足少数民族文字处理需求的字体技术--OpenType.最后,阐述了文字处理引擎的工作原理,以及ICU中如何实现对少数民族文字的支持.

基于OpenType的复杂文本语言处理的研究与实现

某些书写系统的文字(如蒙古文、维文、藏文等)具有比拉丁文字复杂的特性,当计算机在处理这类文字时,运用传统的字体技术(如TrueType)几乎不可能在显现出规范的书写形式的同时,实现对Unicode标准编码的支持.就这个问题介绍一种基于OpenType字体的处理模型.事实证明,这是一种可行的方案.

一种基于谓词规则的复杂文字处理模型

复杂文字在显示输出的过程中,表现出极为复杂的语言特征.为此提出了一种基于谓词规则的复杂文字处理模型,模型以谓词规则的方法给出了复杂文字字形布局特征的形式化描述,按照复杂文字处理的过程,设计了实现该模型的软件体系结构,将复杂文字的语言特征从程序控制逻辑中隔离出来,提高了系统的灵活性,便于增加新的复杂文字的支持.在研制蒙古文、藏文、维吾尔文办公套件的应用中表明,该模型是实用有效的.

一种支持多语言文本布局方向的文档处理模型

文档处理是文字处理的关键组成部分，针对多语言混合排版的需求，本文提出了基于“框”的支持不同方向的多语言文本布局的文档处理模型。该模型把时文本布局方向的处理封装在文档格式化模块中，将多文本布局方向的问题规约为文本布局方向为从左向右（水平）的文档格式化的问题，并设计了多文本布局方向文档格式化的递归算法。该模型可以很好支持包括我国民族文字蒙古文、维吾尔文、藏文在内的各种不同书写方向文字的文本布局。

蒙古文显示在OpenOffice.org办公套件中的实现

蒙古文是一种复杂文字,目前操作系统和办公套件都还不支持蒙古文的显示.OpenOffice.org是可以运行在Linux和Windows上跨平台的办公套件,它分别使用ICU LayoutEngine和Uniscribe进行复杂文字处理.本文以支持蒙古文处理的Linux版本OpenOiffice.org为基础,详细分析了OpenOffice.org在Linux和Windows系统上的复杂文本处理过程,采用Uniscribe与ICU相结合的方案,实现了OpenOffice.org在Windows平台上对蒙古文的显示.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.