Pump-Suppressed Nondegenerate Four-Wave Mixing in a Highly Nonlinear Photonic Crystal Fiber Sagnac Loop

We propose a configuration for suppressing pumps in a broad- and flat-hand tunable nondegenerate four-wave mixing (FWM) wavelength converter. The signal and pumps are coupled into a highly nonlinear photonic crystal fiber symmetrical Sagnac loop. After the FWM wavelength conversion in the loop, the idler is separated from the pumps without a filter. In our experiment, a flat wavelength conversion bandwidth of 36 rim, conversion efficiency of-11 dB., pump-to-signal suppression ratio of 48 dB, and idler-to-pump suppression ratio of 15 dB are achieved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Spectrum shape compression and pedestal elimination employing a Sagnac loop

We report on the experimental demonstration of a spectrum shaping filter, which is formed by inserting a fiber polarization controller (PC) in to a Sagnac loop. Pedestal free and narrow spectrum with line width at 1.4-1.7 nm is obtained, which is advantageous for further power amplification and effective frequency doubling. (C) 2008 Elsevier B.V. All rights reserved.

碳离子辐照诱变产生的甜高粱M2代幼苗对高温胁迫的响应

甜高粱(Sorghum bicolor(L)Moench)"凯勒"种子经不同剂量(0、10Gy、30Gy、50Gy、80Gy)80MeV/u碳离子注入后,其M2代幼苗对40℃高温胁迫作出了不同的响应:株高、叶绿素含量变化不大,相对低剂量(10Gy、30Gy)碳离子处理使M2代幼苗生物量高于对照CK(0Gy)和高剂量(50Gy、80Gy)处理,同时从丙二醛(Malondialdehyde,MDA)和可溶性糖含量的变化来看,30Gy碳离子辐射处理组MDA和可溶性糖含量降低,提高了M2代幼苗的高温抗性。

不同剂量重离子辐照玉米自交系的生物学效应比较

用12C6+和36Ar18+离子束分别辐照玉米自交系干种子和浸泡种子,研究了M1—M3代重离子束辐照的生物学效应。结果表明:种子发芽势和发芽率随辐照剂量的增加而下降,不同生理状态的种子对重离子辐照的敏感性也不同。一般12C6+离子辐照干种子的适宜剂量为20—25 Gy;M1代叶型发生明显的变化,M2代植株在株高、穗位、单株穗数、雄穗花药颜色、粒质、穗行数、粒重和抗性等方面均发生了变化,并产生了许多有益的变异,包括株高和穗位降低、同位多穗、穗行数和粒重增加、粒质由粉质变为硬粒以及抗锈病和红叶病的植株等,有益突变的频率达7.0%—17.9%;在M3代出现能够稳定遗传的,并且光合效率增加的有益突变株。由此可见,重离子束辐照是玉米种质改良的一种高效手段。

Rapid detection of porcine circovirus type 2 by loop-mediated isothermal amplification

A method of loop-mediated isothermal amplification (LAMP) was employed to develop a rapid and simple detection system for porcine circovirus type 2 (PCV2). The amplification could be finished in 60 min under isothermal condition at 64 degrees C by employing a set of four primers targeting the cap gene of PCV2. The LAMP assay showed higher sensitivity than the conventional PCR, with a detection limit of five copies per tube of purified PCV2 genomic DNA. No cross-reactivity was observed from the samples of other related viruses including porcine circovirus type 1 (PCV1), porcine parvovirus (PPV), porcine pseudorabies virus (PRV) and porcine reproductive and respiratory syndrome virus (PRRSV). The detection rate of PCV2 LAMP for 86 clinical samples was 96.5% and appeared greater than that of the PCR method. The LAMP assay reported can provide a rapid yet simple test of PCV2 suitable for laboratory diagnosis and pen-side detection due to ease of operation and the requirement of only a regular water bath or heat block for the reaction. (c) 2008 Elsevier B.V. All rights reserved.

CSRe团簇内靶温度闭环控制器设计；Design of Closed Loop Temperature Controller for CSRe Internal Target System

介绍了国家重大科学工程项目——兰州重离子加速器冷却存储环(HIRFL-CSR)的实验环(CSRe)团簇内靶温度闭环控制器的设计。该控制器给气体喷嘴处测温电阻提供长时间稳定度为0.1%的1mA恒定电流,通过12位ADC得到喷嘴温度,并通过混合信号处理器MSP430F149来实现制冷/加热闭环操作。在多种不同实验气体的情况下,该控制器的温度控制精度小于0.5K。目前,该控制器在现场工作良好。

沈阳城市森林三维绿量测算

为了探讨城市森林三维绿量的测算方式及精度,该文利用2001年8月沈阳市真彩航片和抽样调查,借助ARC/GIS,以“立体量推算立体量”的方法测算沈阳城市森林三维绿量.结果表明,不同城市森林类型的单位面积三维绿量以风景游憩林最高,为5.35 m3/m2,附属林4.93 m3/m2,道路林3.65 m3/m2,生态公益林3.62 m3/m2,生产经营林2.35m3/m2;城市森林分布区的单位面积三维绿量为4.25 m3/m2;城区单位面积城市森林三维绿量为0.35 m3/m2.沈阳城市森林总体三维绿量为161 296 716.85 m3,其中附属林为60 116 966.36 m3,占37.27%,生态公益林43 321 771.43 m3,占26.86%,风景游憩林30 482 879.04 m3,占18.90%,道路林23 841 208.75 m3,占14.78%,生产经营林3 533 891.27 m3,占2.19%.经检验,该方法精度达到85.50%(α=0.05).