The real-time optimisation of DNO owned storage devices on the LV network for peak reduction

Energy storage is a potential alternative to conventional network reinforcementof the low voltage (LV) distribution network to ensure the grid’s infrastructure remainswithin its operating constraints. This paper presents a study on the control of such storagedevices, owned by distribution network operators. A deterministic model predictive control (MPC) controller and a stochastic receding horizon controller (SRHC) are presented, wherethe objective is to achieve the greatest peak reduction in demand, for a given storagedevice specification, taking into account the high level of uncertainty in the prediction of LV demand. The algorithms presented in this paper are compared to a standard set-pointcontroller and bench marked against a control algorithm with a perfect forecast. A specificcase study, using storage on the LV network, is presented, and the results of each algorithmare compared. A comprehensive analysis is then carried out simulating a large number of LV networks of varying numbers of households. The results show that the performance of each algorithm is dependent on the number of aggregated households. However, on a typical aggregation, the novel SRHC algorithm presented in this paper is shown to outperform each of the comparable storage control techniques.

Control methodologies: Peak reduction algorithms for DNO owned storage devices on the Low Voltage network

The Distribution Network Operators (DNOs) role is becoming more difficult as electric vehicles and electric heating penetrate the network, increasing the demand. As a result it becomes harder for the distribution networks infrastructure to remain within its operating constraints. Energy storage is a potential alternative to conventional network reinforcement such as upgrading cables and transformers. The research presented here in this paper shows that due to the volatile nature of the LV network, the control approach used for energy storage has a significant impact on performance. This paper presents and compares control methodologies for energy storage where the objective is to get the greatest possible peak demand reduction across the day from a pre-specified storage device. The results presented show the benefits and detriments of specific types of control on a storage device connected to a single phase of an LV network, using aggregated demand profiles based on real smart meter data from individual homes. The research demonstrates an important relationship between how predictable an aggregation is and the best control methodology required to achieve the objective.

A peak reduction scheduling algorithm for storage devices on the low voltage network

Reinforcing the Low Voltage (LV) distribution network will become essential to ensure it remains within its operating constraints as demand on the network increases. The deployment of energy storage in the distribution network provides an alternative to conventional reinforcement. This paper presents a control methodology for energy storage to reduce peak demand in a distribution network based on day-ahead demand forecasts and historical demand data. The control methodology pre-processes the forecast data prior to a planning phase to build in resilience to the inevitable errors between the forecasted and actual demand. The algorithm uses no real time adjustment so has an economical advantage over traditional storage control algorithms. Results show that peak demand on a single phase of a feeder can be reduced even when there are differences between the forecasted and the actual demand. In particular, results are presented that demonstrate when the algorithm is applied to a large number of single phase demand aggregations that it is possible to identify which of these aggregations are the most suitable candidates for the control methodology.

Histological Outcomes on the Development of New Space-making Devices for Maxillary Sinus Floor Augmentation

Background: Previous studies have pointed out that the mere elevation of the maxillary sinus membrane promotes bone formation without the use of augmentation materials. Purpose: This experimental study aimed at evaluating if the two-stage procedure for sinus floor augmentation could benefit from the use of a space-making device in order to increase the bone volume to enable later implant installation with good primary stability. Materials and Methods: Six male tufted capuchin primates (Cebus apella) were subjected to extraction of the three premolars and the first molar on both sides of the maxilla to create an edentulous area. The sinuses were opened using the lateral bone-wall window technique, and the membrane was elevated. One resorbable space-making device was inserted in each maxillary sinus, and the bone window was returned in place. The animals were euthanatized after 6 months, and biopsy blocks containing the whole maxillary sinus and surrounding soft tissues were prepared for ground sections. Results: The histological examination of the specimens showed bone formation in contact with both the schneiderian membrane and the device in most cases even when the device was displaced. The process of bone formation indicates that this technique is potentially useful for two-stage sinus floor augmentation. The lack of stabilization of the device within the sinus demands further improvement of space-makers for predictable bone augmentation. Conclusions: It is concluded that (1) the device used in this study did not trigger any important inflammatory reaction; (2) when the sinus membrane was elevated, bone formation was a constant finding; and (3) an ideal space-making device should be stable and elevate the membrane to ensure a maintained connection between the membrane and the secluded space.

Influence of quantum-dots density on average in-plane strain of optoelectronic devices investigated by high-resolution X-ray diffraction

High-resolution X-ray diffractometry is used to probe the nature of a diffraction-peak broadening previously noticed in quantum dots (QDs) systems with freestanding InAs islands on top of GaAs (001) substrates [Freitas et al., Phys. Status Solidi (A) 204, 2548 (2007)]. The procedure is hence extended to further investigate the capping process of InAs/GaAs QDs. A direct correlation is established between QDs growth rates and misorientation of lattice-planes at the samples surfaces. This effect provides an alternative too] for studying average strain fields on QDs systems in standard triple axis diffractometers running on X-ray tube sources, which are much more common than synchrotron facilities. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Development of Highly Selective Enzymatic Devices Based on Deposition of Permselective Membranes on Aligned Nanowires

We describe a simple and efficient strategy to fabricate enzymatic devices based on the deposition of glucose oxidase on aligned and highly oriented CoNiMo metallic nanowires. CoNiMo nanowires with an average diameter of 200 nm and length of 50 mu m were electrodeposited on Au-covered alumina substrates via electrodeposition, using alumina membranes as templates. Enzyme-modified electrodes were fabricated via enzyme immobilization using a cross-linker. To minimize nonspecific reactions in the presence of interfering agents, a permselective membrane composed of poly(vinylsulfonic acid) and polyamidoamine dendrimer was deposited via electrostatic interaction. The formation of hydrogen peroxide as a product of the enzymatic reaction was monitored at low overpotential, 0.0 V (vs Ag/AgCl). The detection limit was estimated at 22 mu M under an applied potential of 0.0 V. The apparent Michaelis-Menten constant determined from the Lineweaver-Burke plot was 2 mM.

Electroluminescent devices based on rare-earth tetrakis beta-diketonate complexes

In this paper the synthesis, photo luminescence and electroluminescence investigation of the novel tetrakis beta-diketonate of rare-earth complexes such as M[Eu(dbM)(4)] and M[Tb(acac)(4)] with a variety of cationic ligands, M=Li(+), Na(+) and K(+) have been investigated. The emission spectra of the Eu(3+) and Tb(3+) complexes displayed characteristic narrow bands arising from intraconfigurational transitions of trivalent rare-earth ions and exhibited red color emission for the Eu(3+) ion ((5)D(0) -> F(J), J=0-6) and green for the Tb(3+) ion ((5)D(4) -> (7)F(J), J = 6-0). The lack of the broaden emission bands arising from the ligands suggests the efficient intramolecular energy transfer from the dbm and acac ligands to Eu(3+) and Tb(3+) ions, respectively. In accordance to the expected, the values of PL quantum efficiency (eta) of the emitting (5)D(0) state of the tetrakis(beta-diketonate) complexes of Eu(3+) were higher compared with those tris-complexes. Therefore, organic electroluminescent (EL) devices were fabricated with the structure as follows: indium tin oxide (ITO)/hole transport layer (HTL) NPB or MTCD/emitter layer M[RE(beta-diketonate)(4)] complexes)/Aluminum (Al). All the films were deposited by thermal evaporation carried out in a high vacuum environment system. The OLED light emission was independent of driving voltage, indicating that the combination of charge carriers generates excitons within the M[RE(beta-diketonate)(4)] layers, and the energy is efficiently transferred to RE(3+) ion. As a best result, a pure red and green electroluminescent emission was observed from the Eu(3+) and Tb(3+) devices, confirmed by (X,Y) color coordinates. (C) 2008 Elsevier B.V. All rights reserved.

Fabrication and integration of planar electrodes for contactless conductivity detection on polyester-toner electrophoresis microchips

In this report, we describe the microfabrication and integration of planar electrodes for contactless conductivity detection on polyester-toner (PT) electrophoresis microchips using toner masks. Planar electrodes were fabricated by three simple steps: (i) drawing and laser-printing the electrode geometry on polyester films, (ii) sputtering deposition onto substrates, and (iii) removal of toner layer by a lift-off process. The polyester film with anchored electrodes was integrated to PT electrophoresis microchannels by lamination at 120 degrees C in less than 1 min. The electrodes were designed in an antiparallel configuration with 750 mu m width and 750 gm gap between them. The best results were recorded with a frequency of 400 kHz and 10 V-PP using a sinusoidal wave. The analytical performance of the proposed microchip was evaluated by electrophoretic separation of potassium, sodium and lithium in 150 mu m wide x 6 mu m deep microchannels. Under an electric field of 250 V/cm the analytes were successfully separated in less than 90 s with efficiencies ranging from 7000 to 13 000 plates. The detection limits (S/N = 3) found for K+, Na+, and Li+ were 3.1, 4.3, and 7.2 mu mol/L, respectively. Besides the low-cost and instrumental simplicity, the integrated PT chip eliminates the problem of manual alignment and gluing of the electrodes, permitting more robustness and better reproducibility, therefore, more suitable for mass production of electrophoresis microchips.

Interaction and Persuasion:An analysis of the use of rhetorical devices in Gordon Brown's speech to the Labour Party Conference, on September 25, 2006

This essay has identified and analysed rhetorical devices in Gordon Brown’s speech delivered at the Labour Party conference on September 25, 2006. The aim of the study was to identify specific rhetorical devices which are described as interactional resources, analyse their uses and discuss possible effects that they may have when included in a political speech. The results are based on my own interpretations but are supported by information provided in current literature by analysts and researchers of rhetoric use. The result findings could probably serve as evidence of the need for better understanding of the devices used by politicians in their relentless endeavours to influence audience decisions.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip

The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

Determining the interfacial density of states in metal-insulator-semiconductor devices based on poly(3-hexylthiophene)

Low frequency admittance measurements are used to determine the density of interface states in metal-insulator-semiconductor diodes based on the unintentionally doped, p-type semiconductor poly(3-hexylthiophene). After vacuum annealing at 90 degrees C, interface hole trapping states are shown to be distributed in energy with their density decreasing approximately linearly from similar to 20x10(10) to 5x10(10) cm(-2) eV(-1) over an energy range extending from 0.05 to 0.25 eV above the bulk Fermi level. (c) 2008 American Institute of Physics.

Magnetic field effects on the conductivity of organic bipolar and unipolar devices at room temperature

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Effects of hearing protector devices on speech intelligibility

The purpose of this study was to determine the influence of hearing protection devices (HPDs) on the understanding of speech in young adults with normal hearing, both in a silent situation and in the presence of ambient noise. The experimental research was carried out with the following variables: five different conditions of HPD use (without protectors, with two earplugs and with two earmuffs); a type of noise (pink noise); 4 test levels (60, 70, 80 and 90 dB[A]); 6 signal/noise ratios (without noise, + 5, + 10, zero, - 5 and - 10 dB); 5 repetitions for each case, totalling 600 tests with 10 monosyllables in each one. The variable measure was the percentage of correctly heard words (monosyllabic) in the test. The results revealed that, at the lowest levels (60 and 70 dB), the protectors reduced the intelligibility of speech (compared to the tests without protectors) while, in the presence of ambient noise levels of 80 and 90 dB and unfavourable signal/noise ratios (0, -5 and -10 dB), the HPDs improved the intelligibility. A comparison of the effectiveness of earplugs versus earmuffs showed that the former offer greater efficiency in respect to the recognition of speech, providing a 30% improvement over situations in which no protection is used. As might be expected, this study confirmed that the protectors' influence on speech intelligibility is related directly to the spectral curve of the protector's attenuation. (C) 2003 Elsevier B.V. Ltd. All rights reserved.