The influence of high air entry filter on the testing of unsaturated soils using the axis translation technique

Suction is an important stress variable that is required for reliable predictions of the likely performance of unsaturated soils. The axis translation technique is the best established method of measuring or controlling suction; however, the success of this application is heavily dependent on the rating of the high air entry filter (HAF) and how it is incorporated into the testing system. This paper reports some basic experiments in which samples of unsaturated kaolin were brought to saturation in stages using 5 bar and 15 bar HAFs. The results have shown that the water equilibrium in unsaturated soils is greatly affected by the rating of filters. The findings also suggest that the flow through unsaturated soils is not necessarily governed by the one-dimensional consolidation theory that was developed for saturated soils, and this may be attributed to the bimodal pore size distribution of unsaturated soils.

A high performance IIR digital filter chip

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.

Dynamic State Estimation of Power Systems with Quantization Eects: A Recursive Filter Approach

In this paper, a recursive filter algorithm is developed to deal with the state estimation problem for power systems with quantized nonlinear measurements. The measurements from both the remote terminal units and the phasor measurement unit are subject to quantizations described by a logarithmic quantizer. Attention is focused on the design of a recursive filter such that, in the simultaneous presence of nonlinear measurements and quantization effects, an upper bound for the estimation error covariance is guaranteed and subsequently minimized. Instead of using the traditional approximation methods in nonlinear estimation that simply ignore the linearization errors, we treat both the linearization and quantization errors as norm-bounded uncertainties in the algorithm development so as to improve the performance of the estimator. For the power system with such kind of introduced uncertainties, a filter is designed in the framework of robust recursive estimation, and the developed filter algorithm is tested on the IEEE benchmark power system to demonstrate its effectiveness.

Miniaturised sharp rejection bandpass filter with reconfigurable bandwidth for UWB applications

A novel, compact and highly selective microstrip bandpass filter with bandwidth reconfigurability for ultra-wideband (UWB) applications is presented. The proposed design uses stepped impedance resonator (SIR) for realization of bandpass filter (BPF) and employs a single varactor diode (BB135-NXP) for the purpose of reconfiguring bandwidth. Additionally, to improve the selectivity between passband edges, a cross-coupling between I/O feed lines is introduced which generated pairs of attenuation poles at each side of the passband. Measurements on a fabricated reconfigurable filter confirm the accuracy of the design procedure. Measured responses show good agreement with simulation. The proposed filter is able to achieve significant size reduction (8.5 mm × 7.1 mm excluding the feeding ports) as compared to the conventional bandpass filters with reconfigurable bandwidth.

Median Filter Architecture by Accumulative Parallel Counters

The time to process each of the W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing B-bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

Derivative-free optimization and filter methods to solve nonlinear constrained problems

In real optimization problems, usually the analytical expression of the objective function is not known, nor its derivatives, or they are complex. In these cases it becomes essential to use optimization methods where the calculation of the derivatives, or the verification of their existence, is not necessary: the Direct Search Methods or Derivative-free Methods are one solution. When the problem has constraints, penalty functions are often used. Unfortunately the choice of the penalty parameters is, frequently, very difficult, because most strategies for choosing it are heuristics strategies. As an alternative to penalty function appeared the filter methods. A filter algorithm introduces a function that aggregates the constrained violations and constructs a biobjective problem. In this problem the step is accepted if it either reduces the objective function or the constrained violation. This implies that the filter methods are less parameter dependent than a penalty function. In this work, we present a new direct search method, based on simplex methods, for general constrained optimization that combines the features of the simplex method and filter methods. This method does not compute or approximate any derivatives, penalty constants or Lagrange multipliers. The basic idea of simplex filter algorithm is to construct an initial simplex and use the simplex to drive the search. We illustrate the behavior of our algorithm through some examples. The proposed methods were implemented in Java.

Incremental filter and wrapper approaches for feature discretization

Discrete data representations are necessary, or at least convenient, in many machine learning problems. While feature selection (FS) techniques aim at finding relevant subsets of features, the goal of feature discretization (FD) is to find concise (quantized) data representations, adequate for the learning task at hand. In this paper, we propose two incremental methods for FD. The first method belongs to the filter family, in which the quality of the discretization is assessed by a (supervised or unsupervised) relevance criterion. The second method is a wrapper, where discretized features are assessed using a classifier. Both methods can be coupled with any static (unsupervised or supervised) discretization procedure and can be used to perform FS as pre-processing or post-processing stages. The proposed methods attain efficient representations suitable for binary and multi-class problems with different types of data, being competitive with existing methods. Moreover, using well-known FS methods with the features discretized by our techniques leads to better accuracy than with the features discretized by other methods or with the original features. (C) 2013 Elsevier B.V. All rights reserved.

Assessment of hydrogen sulfide removal from biogas using a field scale anoxic biotrickling filter.

Hydrogen sulphide is one of the most toxic and corrosive compound present in swine-derived biogas streams.In this study, afield scale biotrickling filter for the removal of hydrogen sulfide was investigated.A Biofilter packed with supporting biofilm materials was fed continuously with a proprietary nutrient solution and operatedfor over 73days. The system has been operating with a H2S inlet concentrations ranging from 1,000to 3,000 ppm.Significant removal efficiencies >95% was demonstrated. pH of the stock feeding solution decreased from 6.2 to as low as 3.5within couple days.The resulting drop in pH provided circumstantial evidence to support biological H2 Soxidation to sulphuric acid by sulfide-oxidizers. Sulfur precipitation was also observed to occur. The results suggested that H2S removal from biogas stream can be efficiently achieved using portable, low cost and maintenance free biotrickling filters.

Compact asymmetric coplanar waveguide filter

The design and implementation of a novel asymmetric coplanar waveguide (ACPW ) band rejection filter using defected ground structure ( DGS) is presented . The proposed ACPW DGS technology provides band gap characteristics with only one cell in the lateral ground plane . The equivalent circuit model of the proposed DGS unit section is described . Measurements of ACPW DGS showed good agreement with simulation and the proposed model

Microstrip band rejection filter using open loop resonator

Design of a compact microstrip band reject filter is proposed. The device consists of an Open Loop Rectangular Resonator (OLRR) coupled to a microstrip line. The transmission line has a U-bend which enhances the coupling with the OLRR element and reduces the size of the filter. The filter can be made tunable by mounting variable capacitance to the system. Simulated and experimental results are presented.

SRR loaded waveguide band rejection filter with adjustable bandwidth

The use of a split-ring resonator (SRR)-loaded waveguide for the design of a band-rejection filter with adjustable bandwidth is reported. The width of the stopband can be adjusted by suitably positioning the SRR array in the waveguide. The rejection band can be made very narrow by placing the array at the electric-field minimum. The stopband attenuation depends on the number of unit cells in the array.

Performance analysis of FIR digital filter design: RNS versus traditional

Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated