Centrifugal separation of molten steel and glass mixtures

A lot of mixed vitrified waste exists at DOE sites, which contain valuable metal having great potential for being reused in industry. Of these useful metals, steel constitutes more than 45% of the volume. Using the differential centrifugal separation technology, steel is separated by using remote melting of the mixed waste. The high costs involved are directly proportional to the time involved in separation of the steel from the mixed waste. This is determined by using similitude principles. Having obtained a solidified steel ingot by melting, it is essential to determine the decontaminated portions of the ingot that can be released to industry. Two parameters representing measures of separation are proposed—the Centrifugal Fluid Separation Number and the Thermal Separation Number. Regression correlations are determined to express the estimated time of separation. Experimental analysis of solidified ingots has shown that when the Thermal Separation Number is less than 1700 the steel contains little or no trace of glass. This result can be used to recycle steel back to industry. ^

Evaluation of Two Ultrasonic Systems for Analysis of Porosity in Ceramic

The Ultrasound Laboratory of the Nuclear Engineering Institute (LABUS / IEN) has developed an ultrasonic technique to measure porosity in nuclear fuel pellets (UO2). By difficulties related to the handling of UO2 pellets, Alumina (Al2O3) pellets have been used in preliminary tests, until a methodology for tests with pellets of UO2 could be defined. In a previous work, in which a contact ultrasonic technique was used, good results were obtained to measure the porosity of Alumina pellets. In the current studies, it was found that the frequency spectrum of an ultrasonic pulse is very sensitive to the porosity of the medium in which it propagates. In order to define the most appropriate experimental apparatus for using immersion technique in future tests, two ultrasonic systems, available in LABUS, which permit to work with the ultrasonic pulse in the frequency domain were evaluated . One system was the Explorer II (Matec INSTRUMENTS) and the other the ultrasonic pulse generator Epoch 4 Plus (Panametrics) coupled with an oscilloscope TDS 3032B (Tektronix). For this evaluation, several frequency spectra were obtained with the two equipment, by the passage of the ultrasonic wave in the same pellet of Alumina. This procedure was performed on four different days, on each day 12 ultrasonic signals were acquired, one signal every 10 minutes, with each apparatus. The results were compared and analyzed as regard the repeatability of the frequency spectra obtained.

CHARACTERIZATION OF RADIATION DAMAGE TO A NOVEL PHOTONIC CRYSTAL SENSOR

New methods of nuclear fuel and cladding characterization must be developed and implemented to enhance the safety and reliability of nuclear power plants. One class of such advanced methods is aimed at the characterization of fuel performance by performing minimally intrusive in-core, real time measurements on nuclear fuel on the nanometer scale. Nuclear power plants depend on instrumentation and control systems for monitoring, control and protection. Traditionally, methods for fuel characterization under irradiation are performed using a “cook and look” method. These methods are very expensive and labor-intensive since they require removal, inspection and return of irradiated samples for each measurement. Such fuel cladding inspection methods investigate oxide layer thickness, wear, dimensional changes, ovality, nuclear fuel growth and nuclear fuel defect identification. These methods are also not suitable for all commercial nuclear power applications as they are not always available to the operator when needed. Additionally, such techniques often provide limited data and may exacerbate the phenomena being investigated. This thesis investigates a novel, nanostructured sensor based on a photonic crystal design that is implemented in a nuclear reactor environment. The aim of this work is to produce an in-situ radiation-tolerant sensor capable of measuring the deformation of a nuclear material during nuclear reactor operations. The sensor was fabricated on the surface of nuclear reactor materials (specifically, steel and zirconium based alloys). Charged-particle and mixed-field irradiations were both performed on a newly-developed “pelletron” beamline at Idaho State University's Research and Innovation in Science and Engineering (RISE) complex and at the University of Maryland's 250 kW Training Reactor (MUTR). The sensors were irradiated to 6 different fluences (ranging from 1 to 100 dpa), followed by intensive characterization using focused ion beam (FIB), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) to investigate the physical deformation and microstructural changes between different fluence levels, to provide high-resolution information regarding the material performance. Computer modeling (SRIM/TRIM) was employed to simulate damage to the sensor as well as to provide significant information concerning the penetration depth of the ions into the material.

The dynamic decode-and-forward channel: SNR allocation.

In the half-duplex relay channel applying the decode-and-forward protocol the relay introduces energy over random time intervals into the channel as observed at the destination. Consequently, during simulation the average signal power seen at the destination becomes known at run-time only. Therefore, in order to obtain specific performance measures at the signal-to-noise ratio (SNR) of interest, strategies are required to adjust the noise variance during simulation run-time. It is necessary that these strategies result in the same performance as measured under real-world conditions. This paper introduces three noise power allocation strategies and demonstrates their applicability using numerical and simulation results.

A touchless passive Infrared gesture sensor.

A sensing device for a touchless, hand gesture, user interface based on an inexpensive passive infrared pyroelectric detector array is presented. The 2 x 2 element sensor responds to changing infrared radiation generated by hand movement over the array. The sensing range is from a few millimetres to tens of centimetres. The low power consumption (< 50 μW) enables the sensor’s use in mobile devices and in low energy applications. Detection rates of 77% have been demonstrated using a prototype system that differentiates the four main hand motion trajectories – up, down, left and right. This device allows greater non-contact control capability without an increase in size, cost or power consumption over existing on/off devices.

CFAR Adaptive PN Code acquisition for DSSS Systems.

Constant false alarm rate (CFAR) techniques can be used in Pseudo-Noise (PN) code acquisition in Spread Spectrum (SS) communication systems, and all the CFAR techniques perform well in homogeneous background PN code acquisition. However, in non-homogeneous background, some CFAR techniques suffer rapid degradation. GO/SO (Greatest-of/Smallest-of) CFAR and adaptive censored mean level detector (ACMLD) are two adaptive CFAR techniques, which are analyzed and compared with other CFAR techniques. The simulation results show that GO/SO CFAR is superior to other CFAR techniques, it maintains short mean acquisition time (MAT) even at environment with strong clutter noise, and ACMLD is suitable for background with strong interfering targets

Mid-infrared photonic sensors based on metamaterial structures

In this work three different metallic metamaterials (MMs) structures such as asymmetric split ring resonators (A-SRRs), dipole and split H-shaped (ASHs) structures that support plasmonic resonances have been developed. The aim of the work involves the optimization of photonic sensor based on plasmonic resonances and surface enhanced infrared absorption (SEIRA) from the MM structures. The MMs structures were designed to tune their plasmonic resonance peaks in the mid-infrared region. The plasmonic resonance peaks produced are highly dependent on the structural dimension and polarisation of the electromagnetic (EM) source. The ASH structure particularly has the ability to produce the plasmonic resonance peak with dual polarisation of the EM source. The double resonance peaks produced due to the asymmetric nature of the structures were optimized by varying the fundamental parameters of the design. These peaks occur due to hybridization of the individual elements of the MMs structure. The presence of a dip known as a trapped mode in between the double plasmonic peaks helps to narrow the resonances. A periodicity greater than twice the length and diameter of the metallic structure was applied to produce narrow resonances for the designed MMs. A nanoscale gap in each structure that broadens the trapped mode to narrow the plasmonic resonances was also used. A thickness of 100 nm gold was used to experimentally produce a high quality factor of 18 in the mid-infrared region. The optimised plasmonic resonance peaks was used for detection of an analyte, 17β-estradiol. 17β-estradiol is mostly responsible for the development of human sex organs and can be found naturally in the environment through human excreta. SEIRA was the method applied to the analysis of the analyte. The work is important in the monitoring of human biology and in water treatment. Applying this method to the developed nano-engineered structures, enhancement factors of 10^5 and a sensitivity of 2791 nm/RIU was obtained. With this high sensitivity a figure of merit (FOM) of 9 was also achieved from the sensors. The experiments were verified using numerical simulations where the vibrational resonances of the C-H stretch from 17β-estradiol were modelled. Lastly, A-SRRs and ASH on waveguides were also designed and evaluated. These patterns are to be use as basis for future work.

Spatial and temporal measurements using polyoxometalate, enzymatic and biofilm layers on a CMOS 0.35 μm 64 X 64-pixel I.S.F.E.T. array sensor

This thesis presents the achievements and scientific work conducted using a previously designed and fabricated 64 x 64-pixel ion camera with the use of a 0.35 μm CMOS technology. We used an array of Ion Sensitive Field Effect Transistors (ISFETs) to monitor and measure chemical and biochemical reactions in real time. The area of our observation was a 4.2 x 4.3 mm silicon chip while the actual ISFET array covered an area of 715.8 x 715.8 μm consisting of 4096 ISFET pixels in total with a 1 μm separation space among them. The ion sensitive layer, the locus where all reactions took place was a silicon nitride layer, the final top layer of the austriamicrosystems 0.35 μm CMOS technology used. Our final measurements presented an average sensitivity of 30 mV/pH. With the addition of extra layers we were able to monitor a 65 mV voltage difference during our experiments with glucose and hexokinase, whereas a difference of 85 mV was detected for a similar glucose reaction mentioned in literature, and a 55 mV voltage difference while performing photosynthesis experiments with a biofilm made from cyanobacteria, whereas a voltage difference of 33.7 mV was detected as presented in literature for a similar cyanobacterial species using voltamemtric methods for detection. To monitor our experiments PXIe-6358 measurement cards were used and measurements were controlled by LabVIEW software. The chip was packaged and encapsulated using a PGA-100 chip carrier and a two-component commercial epoxy. Printed circuit board (PCB) has also been previously designed to provide interface between the chip and the measurement cards.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.