Stacked photo-sensing devices based on SiC alloys A non-pixelled architecture for imagers and demultiplexing devices

In this review paper different designs based on stacked p-i'-n-p-i-n heterojunctions are presented and compared with the single p-i-n sensing structures. The imagers utilise self-field induced depletion layers for light detection and a modulated laser beam for sequential readout. The effect of the sensing element structure, cell configurations (single or tandem), and light source properties (intensity and wavelength) are correlated with the sensor output characteristics (light-to-dark sensivity, spatial resolution, linearity and S/N ratio). The readout frequency is optimized showing that scans speeds up to 104 lines per second can be achieved without degradation in the resolution. Multilayered p-i'-n-p-i-n heterostructures can also be used as wavelength-division multiplexing /demultiplexing devices in the visible range. Here the sensor element faces the modulated light from different input colour channels, each one with a specific wavelength and bit rate. By reading out the photocurrent at appropriated applied bias, the information is multiplexed or demultiplexed and can be transmitted or recovered again. Electrical models are present to support the sensing methodologies.

An architecture for an effective usage of data mining in business intelligence systems

Business Intelligence (BI) is one emergent area of the Decision Support Systems (DSS) discipline. Over the last years, the evolution in this area has been considerable. Similarly, in the last years, there has been a huge growth and consolidation of the Data Mining (DM) field. DM is being used with success in BI systems, but a truly DM integration with BI is lacking. Therefore, a lack of an effective usage of DM in BI can be found in some BI systems. An architecture that pretends to conduct to an effective usage of DM in BI is presented.

A Flexible Architecture for the Computation of Direct and Inverse Transforms in H.264/AVC Video Codecs

A new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of theproposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).

Using an ambient intelligent architecture for developing an intelligent tutoring system for training operators of power system control centres

This paper describes an architecture conceived to integrate Power Sys-tems tools in a Power System Control Centre, based on an Ambient Intelligent (AmI) paradigm. This architecture is an instantiation of the generic architecture proposed in [1] for developing systems that interact with AmI environments. This architecture has been proposed as a consequence of a methodology for the inclu-sion of Artificial Intelligence in AmI environments (ISyRAmI - Intelligent Sys-tems Research for Ambient Intelligence). The architecture presented in the paper will be able to integrate two applications in the control room of a power system transmission network. The first is SPARSE expert system, used to get diagnosis of incidents and to support power restoration. The second application is an Intelligent Tutoring System (ITS) incorporating two training tools. The first tutoring tool is used to train operators to get the diagnosis of incidents. The second one is another tutoring tool used to train operators to perform restoration procedures.

Optimal intelligent supervisory control system in cyber-physical intelligence

This paper studies Optimal Intelligent Supervisory Control System (OISCS) model for the design of control systems which can work in the presence of cyber-physical elements with privacy protection. The development of such architecture has the possibility of providing new ways of integrated control into systems where large amounts of fast computation are not easily available, either due to limitations on power, physical size or choice of computing elements.

Personality, emotion, and mood in agent-based group decision making

Group decision making plays an important role in organizations, especially in the present-day economy that demands high-quality, yet quick decisions. Group decision-support systems (GDSSs) are interactive computer-based environments that support concerted, coordinated team efforts toward the completion of joint tasks. The need for collaborative work in organizations has led to the development of a set of general collaborative computer-supported technologies and specific GDSSs that support distributed groups (in time and space) in various domains. However, each person is unique and has different reactions to various arguments. Many times a disagreement arises because of the way we began arguing, not because of the content itself. Nevertheless, emotion, mood, and personality factors have not yet been addressed in GDSSs, despite how strongly they influence results. Our group’s previous work considered the roles that emotion and mood play in decision making. In this article, we reformulate these factors and include personality as well. Thus, this work incorporates personality, emotion, and mood in the negotiation process of an argumentbased group decision-making process. Our main goal in this work is to improve the negotiation process through argumentation using the affective characteristics of the involved participants. Each participant agent represents a group decision member. This representation lets us simulate people with different personalities. The discussion process between group members (agents) is made through the exchange of persuasive arguments. Although our multiagent architecture model4 includes two types of agents—the facilitator and the participant— this article focuses on the emotional, personality, and argumentation components of the participant agent.

An architecture for ambient intelligent environments

This paper presents the proposal of an architecture for developing systems that interact with Ambient Intelligence (AmI) environments. This architecture has been proposed as a consequence of a methodology for the inclusion of Artificial Intelligence in AmI environments (ISyRAmI - Intelligent Systems Research for Ambient Intelligence). The ISyRAmI architecture considers several modules. The first is related with the acquisition of data, information and even knowledge. This data/information knowledge deals with our AmI environment and can be acquired in different ways (from raw sensors, from the web, from experts). The second module is related with the storage, conversion, and handling of the data/information knowledge. It is understood that incorrectness, incompleteness, and uncertainty are present in the data/information/knowledge. The third module is related with the intelligent operation on the data/information/knowledge of our AmI environment. Here we include knowledge discovery systems, expert systems, planning, multi-agent systems, simulation, optimization, etc. The last module is related with the actuation in the AmI environment, by means of automation, robots, intelligent agents and users.

Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

An ultrasound based computer-aided diagnosis tool for steatosis detection

Liver steatosis is a common disease usually associated with social and genetic factors. Early detection and quantification is important since it can evolve to cirrhosis. In this paper, a new computer-aided diagnosis (CAD) system for steatosis classification, in a local and global basis, is presented. Bayes factor is computed from objective ultrasound textural features extracted from the liver parenchyma. The goal is to develop a CAD screening tool, to help in the steatosis detection. Results showed an accuracy of 93.33%, with a sensitivity of 94.59% and specificity of 92.11%, using the Bayes classifier. The proposed CAD system is a suitable graphical display for steatosis classification.

Explorador integrado de serviços de armazenamento na cloud: cloud cockpit

Projeto para obtenção do grau de Mestre em Engenharia Informática e de Computadores

Projeto de estrutura variante de um edifício de escritórios em Lisboa

Trabalho de Projecto para obtenção do grau de Mestre em Engenharia Civil na Área de Especialização de Estruturas

Controlador Boundary-Scan

A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

Avaliação da caracterização de lesões em mamografia com recurso a sistemas CAD (Computer-Aided Diagnosis)

Os sistemas Computer-Aided Diagnosis (CAD) auxiliam a deteção e diferenciação de lesões benignas e malignas, aumentando a performance no diagnóstico do cancro da mama. As lesões da mama estão fortemente correlacionadas com a forma do contorno: lesões benignas apresentam contornos regulares, enquanto as lesões malignas tendem a apresentar contornos irregulares. Desta forma, a utilização de medidas quantitativas, como a dimensão fractal (DF), pode ajudar na caracterização dos contornos regulares ou irregulares de uma lesão. O principal objetivo deste estudo é verificar se a utilização concomitante de 2 (ou mais) medidas de DF – uma tradicionalmente utilizada, a qual foi designada por “DF de contorno”; outra proposta por nós, designada por “DF de área” – e ainda 3 medidas obtidas a partir destas, por operações de dilatação/erosão e por normalização de uma das medidas anteriores, melhoram a capacidade de caracterização de acordo com a escala BIRADS (Breast Imaging Reporting and Data System) e o tipo de lesão. As medidas de DF (DF contorno e DF área) foram calculadas através da aplicação do método box-counting, diretamente em imagens de lesões segmentadas e após a aplicação de um algoritmo de dilatação/erosão. A última medida baseia-se na diferença normalizada entre as duas medidas DF de área antes e após a aplicação do algoritmo de dilatação/erosão. Os resultados demonstram que a medida DF de contorno é uma ferramenta útil na diferenciação de lesões, de acordo com a escala BIRADS e o tipo de lesão; no entanto, em algumas situações, ocorrem alguns erros. O uso combinado desta medida com as quatro medidas propostas pode melhorar a classificação das lesões.

A Compact and Scalable RNS Architecture

Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013