936 resultados para Architectures profondes
Resumo:
20th International Conference on Reliable Software Technologies - Ada-Europe 2015 (Ada-Europe 2015), Madrid, Spain.
Resumo:
20th International Conference on Reliable Software Technologies - Ada-Europe 2015 (Ada-Europe 2015), 22 to 26, Jun, 2015, Madrid, Spain.
Resumo:
In this work a forest fire detection solution using small autonomous aerial vehicles is proposed. The FALCOS unmanned aerial vehicle developed for remote-monitoring purposes is described. This is a small size UAV with onboard vision processing and autonomous flight capabilities. A set of custom developed navigation sensors was developed for the vehicle. Fire detection is performed through the use of low cost digital cameras and near-infrared sensors. Test results for navigation and ignition detection in real scenario are presented.
Resumo:
Proceedings of the Scientific Meeting of the Portuguese Robotics Open 2004
Resumo:
Poster presented in 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 25 to 28, Mar, 2015, Poster Session. Porto, Portugal.
Resumo:
23rd International Conference on Real-Time Networks and Systems (RTNS 2015). 4 to 6, Nov, 2015, Main Track. Lille, France. Best Paper Award Nominee
Resumo:
Article in Press, Corrected Proof
Resumo:
13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2015). 21 to 23, Oct, 2015, Session W1-A: Multiprocessing and Multicore Architectures. Porto, Portugal.
Resumo:
Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 2013
Resumo:
Presented at SEMINAR "ACTION TEMPS RÉEL:INFRASTRUCTURES ET SERVICES SYSTÉMES". 10, Apr, 2015. Brussels, Belgium.
Resumo:
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.
Resumo:
Presented at INForum - Simpósio de Informática (INFORUM 2015). 7 to 8, Sep, 2015. Portugal.
Resumo:
The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. The advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictable high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. To this end, it is of paramount importance to develop new techniques for exploiting the massively parallel computation capabilities of such platforms in a predictable way. P-SOCRATES will tackle this important challenge by merging leading research groups from the HPC and EC communities. The time-criticality and parallelisation challenges common to both areas will be addressed by proposing an integrated framework for executing workload-intensive applications with real-time requirements on top of next-generation commercial-off-the-shelf (COTS) platforms based on many-core accelerated architectures. The project will investigate new HPC techniques that fulfil real-time requirements. The main sources of indeterminism will be identified, proposing efficient mapping and scheduling algorithms, along with the associated timing and schedulability analysis, to guarantee the real-time and performance requirements of the applications.
Resumo:
In order to increase the efficiency in the use of energy resources, the electrical grid is slowly evolving into a smart(er) grid that allows users' production and storage of energy, automatic and remote control of appliances, energy exchange between users, and in general optimizations over how the energy is managed and consumed. One of the main innovations of the smart grid is its organization over an energy plane that involves the actual exchange of energy, and a data plane that regards the Information and Communication Technology (ICT) infrastructure used for the management of the grid's data. In the particular case of the data plane, the exchange of large quantities of data can be facilitated by a middleware based on a messaging bus. Existing messaging buses follow different data management paradigms (e.g.: request/response, publish/subscribe, data-oriented messaging) and thus satisfy smart grids' communication requirements at different extents. This work contributes to the state of the art by identifying, in existing standards and architectures, common requirements that impact in the messaging system of a data plane for the smart grid. The paper analyzes existing messaging bus paradigms that can be used as a basis for the ICT infrastructure of a smart grid and discusses how these can satisfy smart grids' requirements.
Resumo:
Dissertation presented to obtain the degree of Doctor in Electrical and Computer Engineering, specialization on Collaborative Enterprise Networks