Global down-regulation of HOX gene expression in PML-RAR alpha(+) acute promyelocytic leukemia identified by small-array real-time PCR

Acute promyelocytic leukemia (APL) is associated with a reciprocal and balanced translocation involving the retinoic acid receptor-alpha (RARalpha). All-trans retinoic acid (ATRA) is used to treat APL and is a potent morphogen that regulates HOX gene expression in embryogenesis and organogenesis. HOX genes are also involved in hematopoiesis and leukemogenesis. Thirty-nine mammalian HOX genes have been identified and classified into 13 paralogous groups clustered on 4 chromosomes. They encode a complex net-Work of transcription regulatory proteins whose precise targets remain poorly understood. The overall function of the network appears to be dictated by gene dosage. To investigate the mechanisms involved in HOX gene regulation in hematopoiesis and leukemogenesis by precise measurement of individual HOX genes, a small-array real-time HOX (SMART-HOX) quantitative polymerase chain reaction (PCR) platform was designed and validated. Application of SMART-HOX to 16 APL bone marrow samples revealed a global down-regulation of 26 HOX genes compared with normal controls. HOX gene expression was also altered during differentiation induced by ATRA in the PML-RARalpha(+) NB4 cell line. PML-RARalpha, fusion proteins have been reported to act as part of a repressor complex during myelold cell differentiation, and a model linking HOX gene expression to this PML-RARalpha repressor complex is now proposed.

A one pot three-step process for the synthesis of an array of arylated benzimidazoribosyl nucleosides

A three-step one pot reaction/purification protocol was developed to facilitate rapid access to benzimidazole-based nucleosides, for which benzoylated benzimidazoribosyl nucleosides incorporating boronic esters were key reaction intermediates.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with runtime reconfigurability. We present a softcore-processor based solution to this issue, and show for the first time, that such programmable architectures can enable real-time data operation for cutting-edge standards
such as 802.11n; furthermore, by exploiting deep processing pipelines and interleaved task execution, the cost and performance of these architectures is shown to be on a par with traditional dedicated circuit based solutions. We believe this to be the first such programmable architecture to achieve this, and the combination of implementation efficiency and programmability makes this implementation style the most promising approach for hosting such dynamic architectures.

Electromagnetic wave diffraction from an infinite array of complex-shaped microstrip reflectors

A numerical-analytical method is developed for solving surface integral equations (IEs) describing electromagnetic wave diffraction from arrays of complex-shaped planar reflectors. Solutions to these equations are regularized via analytical transformation of the separated singular part of the matrix kernel. Basis functions satisfying the metal-edge condition are determined on the entire surface of the complex region. The amplitude and phase responses of arrays consisting of polygonal reflectors are numerically investigated.

QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.