868 resultados para PARALLEL WORKSTATIONS
Resumo:
This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.
Resumo:
This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.
Resumo:
This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.
Resumo:
Seed bubbles are generated on microheaters located at the microchannel upstream and driven by a pulse voltage signal, to improve flow and heat transfer performance in microchannels. The present study investigates how seed bubbles stabilize flow and heat transfer in micro-boiling systems. For the forced convection flow, when heat flux at the wall surface is continuously increased, flow instability is self-sustained in microchannels with large oscillation amplitudes and long periods. Introduction of seed bubbles in time sequence improves flow and heat transfer performance significantly. Low frequency (similar to 10 Hz) seed bubbles not only decrease oscillation amplitudes of pressure drops, fluid inlet and outlet temperatures and heating surface temperatures, but also shorten oscillation cycle periods. High frequency (similar to 100 Hz or high) seed bubbles completely suppress the flow instability and the heat transfer system displays stable parameters of pressure drops, fluid inlet and outlet temperatures and heating surface temperatures. Flow visualizations show that a quasi-stable boundary interface from spheric bubble to elongated bubble is maintained in a very narrow distance range at any time. The seed bubble technique almost does not increase the pressure drop across microsystems, which is thoroughly different from those reported in the literature. The higher the seed bubble frequency, the more decreased heating surface temperatures are. A saturation seed bubble frequency of 1000-2000 Hz can be reached, at which heat transfer enhancement attains the maximum degree, inferring a complete thermal equilibrium of vapor and liquid phases in microchannels. Benefits of the seed bubble technique are the stabilization of flow and heat transfer, decreasing heating surface temperatures and improving temperature uniformity of the heating surface.
Resumo:
Transient flow patterns and bubble slug lengths were investigated with oxygen gas (O-2) bubbles produced by catalytic chemical reactions using a high speed camera bonded with a microscope. The microreactor consists of an inlet liquid plenum, nine parallel rectangular microchannels followed by a micronozzle, using the MEMS fabrication technique. The etched surface was deposited by the thin platinum film, which is acted as the catalyst. Experiments were performed with the inlet mass concentration of the hydrogen peroxide from 50% to 90% and the pressure drop across the silicon chip from 2.5 to 20.0 kPa. The silicon chip is directly exposed in the environment thus the heat released via the catalytic chemical reactions is dissipated into the environment and the experiment was performed at the room temperature level. It is found that the two-phase flow with the catalytic chemical reactions display the cyclic behavior. A full cycle consists of a short fresh liquid refilling stage, a liquid decomposition stage followed by the bubble slug flow stage. At the beginning of the bubble slug flow stage, the liquid slug number reaches maximum, while at the end of the bubble slug flow stage the liquid slugs are quickly flushed out of the microchannels. Two or three large bubbles are observed in the inlet liquid plenum, affecting the two-phase distributions in microchannels. The bubble slug lengths, cycle periods as well as the mass flow rates are analyzed with different mass concentrations of hydrogen peroxide and pressure drops. The bubble slug length is helpful for the selection of the future microreactor length ensuring the complete hydrogen peroxide decomposition. Future studies on the temperature effect on the transient two-phase flow with chemical reactions are recommended.