924 resultados para DC links


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A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

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This paper describes a solid state electrical emulator devised for laboratory testing of power conditioning electronics for direct drive linear wave energy converters (DDLWEC). Two rectification strategies are considered; a uni-directional boost topology, and an H-bridge which may be controlled in either uni- or bidirectional modes.

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In order to design a High Temperature Superconducting (HTS) machine that is able to operate safely and reliably, studies on the characterization of Second Generation (2G) HTS tapes are of paramount importance. This paper presents an experimental setup to measure critical current of 2G HTS tapes in high DC magnetic fields (up to 5 Tesla) with an AC current ripple superimposed, as well as various temperatures ranging from 25 K to 77 K. The 2G tape measured is the SGS12050 coated conductor made by SuperPower. The critical current is measured by a flux vector with reference to the widest sample face from 0 to 90 degrees in 10 degree steps. Smaller steps are required close to 0 . A Variable Temperature Insert (VTI) is utilized to control temperature change. © 2010 IEEE.

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The karyotype of Indian muntjacs (Muntiacus muntjak vaginalis) has been greatly shaped by chromosomal fusion, which leads to its lowest diploid number among the extant known mammals. We present, here, comparative results based on draft sequences of 37 bac

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The impact of Adaptive Cyclic Prefix (ACP) on the transmission performance of Adaptively Modulated Optical OFDM (AMOOFDM) is explored thoroughly in directly modulated DFB laser-based, IMDD links involving Multimode Fibres (MMFs)/Single-Mode Fibres (SMFs). Three ACP mechanisms are identified, each of which can, depending upon the link properties, affect significantly the AMOOFDM transmission performance. In comparison with AMOOFDM having a fixed cyclic prefix duration of 25%, AMOOFDM with ACP can not only improve the transmission capacity by a factor of >2 (>1.3) for >1000 m MMFs (<80 km SMFs) with 1 dB link loss margin enhancement, but also relax considerably the requirement on the DFB bandwidth.

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Detailed investigations are undertaken, for the first time, of the transmission performance of recently proposed novel Adaptively Modulated Optical OFDM (AMOOFDM) modems using Subcarrier Modulation (AMOOFDM-SCM) in single-channel, SMF-based IMDD links without optical amplification and chromatic dispersion compensation. The cross-talk effect induced by beatings among subcarriers of various types is a crucial factor limiting the maximum achievable AMOOFDM-SCM performance. By applying single sideband modulation and/or spectral gapping to AMOOFDM-SCM, three AMOOFDM-SCM designs of varying complexity are proposed, which achieve >60Gb/s signal transmission over 20 km, 40 km and 60 km. Such performances are >1.5 times higher than those supported by conventional AMOOFDM modems.

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Orthogonal multipulse modulation is demonstrated to allow ≈30 Gb/s real-time transmission over multimode fibre using an 850 nm VCSEL. The scheme eases considerably component bandwidth requirements compared with conventional NRZ modulation. © 2011 OSA.

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This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.

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Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

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The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.

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Simulations have been performed to compare the system capacity and power dissipation of NRZ, CAP-64 and 64-QAM-OFDM systems over FEC enhanced POF links using LEDs, for both unidirectional and bidirectional transmission. It is shown that CAP-64 outperforms NRZ and 64-QAM-OFDM in terms of system capacity and supports a record high 3.5Gb/s bidirectional and 2.1Gb/s unidirectional transmissions over 50m POF. The CAP-64 transceiver consumes similar power compared with NRZ whilst the 64-QAM-OFDM transceiver consumes about twice as much. © 2012 Optical Society of America.