Desenvolvimento e implementação de um sintetizador de frequência CMOS utilizando sistema digital

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Projeto de um Multiplicador Divisor Anal´ogico em tecnologia CMOS para uso em controlador fuzzy tipo-2 intervalar

The main objective of the presented study is the design of a analog multiplier-divider as integrant part of the type-reducer circuit of type-2 fuzzy controller chip. The proposed circuit is a multiplier/divider which operates in current mode, in the CMOS technology with a supply voltage of 1.8 V.The circuit simulation was performed in PSPICE software with simulation model provided by AMS (Austria Mikro Systems International) in CMOS technology 0.35μm

Conversor analógico digital de 10 bits utilizando arquitetura pipeline e tecnologia CMOS

Pós-graduação em Engenharia Elétrica - FEIS

A Low Power CMOS Voltage Regulator for a Wireless Blood Pressure Biosensor

This paper describes a CMOS implementation of a linear voltage regulator (LVR) used to power up implanted physiological signal systems, as it is the case of a wireless blood pressure biosensor. The topology is based on a classical structure of a linear low-dropout regulator. The circuit is powered up from an RF link, thus characterizing a passive radio frequency identification (RFID) tag. The LVR was designed to meet important features such as low power consumption and small silicon area, without the need for any external discrete components. The low power operation represents an essential condition to avoid a high-energy RF link, thus minimizing the transmitted power and therefore minimizing the thermal effects on the patient's tissues. The project was implemented in a 0.35-mu m CMOS process, and the prototypes were tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA at 37 degrees C. The load regulation is 13 mV/mA, and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.

Development of a slow-wave MEMS phase shifter on CMOS technology for millimeter wave frequencies

We propose a slow-wave MEMS phase shifter that can be fabricated using the CMOS back-end and an additional maskless post-process etch. The tunable phase shifter concept is formed by a conventional slow-wave transmission line. The metallic ribbons that form the patterned floating shield of this type of structure are released to allow motion when a control voltage is applied, which changes the characteristic impedance and the phase velocity. For this device a quality factor greater than 40 can be maintained, resulting in a figure of merit on the order of 0.7 dB/360 degrees and a total area smaller than 0.14 mm(2) for a 60-GHz working frequency. (C) 2011 Elsevier B.V. All rights reserved.

A complete CMOS UWB timed-array transmitter with a 3D Vivaldi antenna array for electronic high-resolution beam spatial scanning

We present a new Ultra Wide Band (UWB) Timed- Array Transmitter System with Beamforming capability for high-resolution remote acquisition of vital signals. The system consists of four identical channels, where each is formed of a serial topology with three modules: programmable delay circuit (PDC or τ), a novel UWB 5th Gaussian Derivative order pulse generator circuit (PG), and a planar Vivaldi antenna. The circuit was designed using 0.18μm CMOS standard process and the planar antenna array was designed with filmconductor on Rogers RO3206 substrate. Spice simulations results showed the pulse generation with 104 mVpp amplitude and 500 ps width. The power consumption is 543 μW, and energy consumption 0.27 pJ per pulse using a 2V power supply at a pulse repetition rate (PRR) of 100 MHz. Electromagnetic simulations results, using CST Microwave (MW) Studio 2011, showed the main lobe radiation with a gain maximum of 13.2 dB, 35.5º x 36.7º angular width, and a beam steering between 17º and -11º for azimuthal (θ) angles and 17º and -18º for elevation (φ) angles at the center frequency of 6 GHz

Diseño de un Amplificador de Bajo Ruido de Ultra Banda Ancha para un Receptor de UWB en CMOS 0.35 μm

Presentación del Proyecto Fin de Carrera titulado "Diseño de un Amplificador de Bajo Ruido de Ultra Banda Ancha para un Receptor de UWB en CMOS 0.35 μm"

Diseño, medida y verificación de un mezclador en CMOS 0.35 um para un receptor basado en el estándar IEEE 802.11a

Proyecto y presentación del Proyecto Fin de Carrera titulado "Diseño, medida y verificación de un mezclador en CMOS 0.35 um para un receptor basado en el estándar IEEE 802.11a"

Diseño de un mezclador pasivo en CMOS 0.35 um para un receptor basado en el estándar IEE802.11a

Memoria y presentación del Proyecto Fin de Carrera titulado "Diseño de un mezclador pasivo en CMOS 0.35 um para un receptor basado en el estándar IEE802.11a"

Diseño de un amplificador operacional totalmente integrado CMOS que funcione como driver para cargas capacitivas elevadas

Presentación del Proyecto Fin de Carrera titulado "Diseño de un Amplificador Operacional totalmente integrado CMOS que funcione como driver para cargas capacitivas elevadas"

Diseño de un convertidor de corriente en tecnología CMOS 0.35

Proyecto y presentación del Proyecto Fin de Carrera titulado "Diseño de un convertidor de corriente en tecnología CMOS 0.35"

Diseño del Amplificador de Bajo Ruido y del Mezclador para un Receptor de UWB en CMOS 0.18um

Especialidad: Sistemas electrónicos

Diseño de un mezclador basado en convertidores de corriente en tecnología CMOS 0.18UM

Proyecto y presentación del Proyecto Fin de Carrera titulado "DISEÑO DE UN MEZCLADOR BASADO EN CONVERTIDORES DE CORRIENTE EN TECNOLOGÍA CMOS 0.18UM"

Diseño de un filtro integrado sintonizable en tecnología CMOS 0.35μm

Especialidad: Sistemas Electrónicos