Computing abuse related damages in the case of new entry: An illustration for the Directory Enquiry Services market

A number of European countries, among which the UK and Spain, have opened up their Directory Enquiry Services (DQs, or 118AB) market to competition. We analyse the Spanish case, where both local and foreign firms challenged the incumbent as of April 2003. We argue that the incumbent had the ability to abuse its dominant position, and that it was a perfectly rational strategy. In short,the incumbent raised its rivals' costs directly by providing an inferior quality version of the (essential) input, namely the incumbent's subscribers' database. We illustrate how it is possible to quantify the effect of abuse in situation were the entrant has no previous history in the market. To do this, we use the UK experience to construct the relevant counterfactual, that is the "but for abuse" scenario. After controlling for relative prices and advertising intensity, we find that one of the foreign entrants achieved a Spanish market share of only half of what it would have been in the absence of abuse.

Report on the Management and Administrative Computing Initiative - Vol II

UNIVERSITY GRANTS COMMITTEE REPORT ON THE INITIATIVE ON MANAGEMENT A~D ADMINISTRATIVE COMPUTING VOLUME II - REFERENCE MANUAL

REPORT ON THE INITIATIVE ON MANAGEMENT AND ADMINISTRATIVE COMPUTING VOLUME II

UNIVERSITY GRANTS COMMITTEE REPORT ON THE INITIATIVE ON MANAGEMENT AND ADMINISTRATIVE COMPUTING VOLUME II - REFERENCE MANUAL

Cloud computing for research - final report

Curtis+Cartwright Consulting Ltd, working with the University of Surrey and Professor Charles Oppenheim, has been commissioned by Jisc to investigate Cloud Computing for Research. This document is the final report, and is accompanied by a briefing paper which provides advice targeted at researchers.

Review of the environmental and organisational implications of cloud computing in higher and further education

The review of the environmental and organisational implications of cloud computing in higher and further education was commissioned by Jisc as part of its green ICT programme.

Astrophysics and Distributed Research utilising Advanced Computing (DiRAC)

Supporting presentation slides to accompany the Janet network end to end performance initiative workshop

NOx emission and thermal efficiency of a 300 MWe utility boiler retrofitted by air staging

Full-scale experiments were performed on a 300 MWe utility boiler retrofitted with air staging. In order to improve boiler thermal efficiency and to reduce NOx emission, the influencing factors including the overall excessive air ratio, the secondary air distribution pattern, the damper openings of CCOFA and SOFA, and pulverized coal fineness were investigated. Through comprehensive combustion adjustment, NOx emission decreased 182 ppm (NOx reduction efficiency was 44%), and boiler heat efficiency merely decreased 0.21%. After combustion improvement, high efficiency and low NOx emission was achieved in the utility coal-fired boiler retrofitted with air staging, and the unburned carbon in ash can maintain at a desired level where the utilization of fly-ash as byproducts was not influenced.

Dense, efficient chip-to-chip communication at the extremes of computing

The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether this is to push data from node-to-node in a high-performance computing cluster or from the receiver of wireless link to a neural stimulator in a biomedical implant, interconnect can take up a significant portion of the overall system power budget. Although a single interconnect methodology cannot address such a broad range of systems efficiently, there are a number of key design concepts that enable good interconnect design in the age of highly-scaled CMOS: an emphasis on highly-digital approaches to solving ‘analog’ problems, hardware sharing between links as well as between different functions (such as equalization and synchronization) in the same link, and adaptive hardware that changes its operating parameters to mitigate not only variation in the fabrication of the link, but also link conditions that change over time. These concepts are demonstrated through the use of two design examples, at the extremes of the power and performance spectra.

A novel all-digital clock and data recovery technique for high-performance, high density interconnect has been developed. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data, while the other is swept across the delay line. The samples produced by the two clocks are compared to generate eye information, which is used to determine the best phase for data recovery. The functions of the two clocks are swapped after the data phase is updated; this ping-pong action allows an infinite delay range without the use of a PLL or DLL. The scheme's generalized sampling and retiming architecture is used in a sharing technique that saves power and area in high-density interconnect. The eye information generated is also useful for tuning an adaptive equalizer, circumventing the need for dedicated adaptation hardware.

On the other side of the performance/power spectra, a capacitive proximity interconnect has been developed to support 3D integration of biomedical implants. In order to integrate more functionality while staying within size limits, implant electronics can be embedded onto a foldable parylene (‘origami’) substrate. Many of the ICs in an origami implant will be placed face-to-face with each other, so wireless proximity interconnect can be used to increase communication density while decreasing implant size, as well as facilitate a modular approach to implant design, where pre-fabricated parylene-and-IC modules are assembled together on-demand to make custom implants. Such an interconnect needs to be able to sense and adapt to changes in alignment. The proposed array uses a TDC-like structure to realize both communication and alignment sensing within the same set of plates, increasing communication density and eliminating the need to infer link quality from a separate alignment block. In order to distinguish the communication plates from the nearby ground plane, a stimulus is applied to the transmitter plate, which is rectified at the receiver to bias a delay generation block. This delay is in turn converted into a digital word using a TDC, providing alignment information.

Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.