An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

Reconstrução de Imagem em SPECT utilizando um colimador convergente e detectores de imagem pixelizados

Dissertação para obtenção do Grau de Mestre em Engenharia Biomédica

Melhoria contínua na gestão de projectos: desenvolvimento e aplicação da ferramenta MAPEA

Dissertação para obtenção do Grau de Mestre em Engenharia e Gestão Industrial

Design of a power output stage for a class D audio power amplifier based on an 1.5-bit ∑ ∆ M

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Transimpedance amplifier for integrated SpO2 optic sensor

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

A 1.2 V low noise amplifier with double feedback for high gain and low noise figure

Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e de Computadores

A low-voltage RF-CMOS receiver front-end for a wireless fall detection microsystem

Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e de Computadores, pela Universidade Nova de Ciências e Tecnologia

Avaliação do ciclo de vida do sistema de produção soja-girassol no cerrado Brasileiro.

RESUMO: O girassol é uma importante cultura na região de Parecis, no Cerrado brasileiro. Em 2014, a região respondeu pela produção de 232.700 t de grãos, 45% da produção nacional. A produção de girassol provém principalmente de um sistema que tem a soja como cultura principal. A associação entre soja e girassol pode reduzir impactos ambientais devido ao uso compartilhado de recursos. Este estudo desenvolveu uma Avaliação de Ciclo de Vida (ACV) ?do berço ao túmulo? do sistema de produção soja-girassol usado na região de Parecis e comparou seu perfil ambiental ao das monoculturas de soja e girassol. Impactos relacionados ao uso do solo (emissões da mudança de uso da terra e calagem) por cada cultura foram alocados em função do tempo de ocupação do solo. O sistema soja-girassol teve impactos ambientais menores em todas as categorias de impacto quando comparado à monocultura de soja e girassol, com o mesmo rendimento. Reduções importantes foram observadas em ?Mudança do Clima?, ?Acidificação Terrestre? e ?Formação de Material Particulado?. ABSTRACT: Sunflower is an important crop in Parecis region of the Brazilian Cerrado. In 2014 the region accounted for the production of 232,700 tons of sunflower grain, 45% of national production. Sunflower production comes mostly from a system that has soybean as the main crop. The association of soybean and sunflower can reduce environmental impacts due to shared use of resources. This study performed a ?cradle to gate? Life Cycle Assessment (LCA) of the soybean-sunflower production system used in Parecis region and compared its environmental profile to that of the monoculture of these two crops. Impacts related to the use of soil (land use change emissions and liming) by each crop were evaluated according to time of soil occupation criterion. Soybean-sunflower system had lower environmental impacts on every impact category comparing to soybean and sunflower monoculture with the same yield. Important reduction were observed on ?Climate change?, ?Terrestrial acidification? and ?Particulate matter formation? categories.

Transimpedance amplifier for early detection of breast cancer

Breast cancer is the most common type of cancer worldwide. The effectiveness of its treatment depends on early stage detection, as well as on the accuracy of its diagnosis. Recently, diagnosis techniques have been submitted to relevant breakthroughs with the upcoming of Magnetic Resonance Imaging, Ultrasound Sonograms and Positron Emission Tomography (PET) scans, among others. The work presented here is focused on studying the application of a PET system to a Positron Emission Mammography (PEM) system. A PET/PEM system works under the principle that a scintillating crystal will detect a gamma-ray pulse, originated at the cancerous cells, converting it into a correspondent visible light pulse. The latter must then be converted into an electrical current pulse by means of a Photo- -Sensitive Device (PSD). After the PSD there must be a Transimpedance Amplifier (TIA) in order to convert the current pulse into a suitable output voltage, in a time period lower than 40 ns. In this Thesis, the PSD considered is a Silicon Photo-Multiplier (SiPM). The usage of this recently developed type of PSD is impracticable with the conventional TIA topologies, as it will be proven. Therefore, the usage of the Regulated Common-Gate (RCG) topology will be studied in the design of the amplifier. There will be also presented two RCG variations, comprising a noise response improvement and differential operation of the circuit. The mentioned topology will also be tested in a Radio-Frequency front-end, showing the versatility of the RCG. A study comprising a low-voltage self-biasing feedback TIA will also be shown. The proposed circuits will be simulated with standard CMOS technology (UMC 130 nm), using a 1.2 V power supply. A power consumption of 0.34 mW with a signal-to-noise ratio of 43 dB was achieved.

Towards printed carbon nanotube transistors on paper substrates

This thesis reports the work performed in the optimization of deposition parameters of Multi – Walled Carbon Nanotubes (MWCNT) targeting the development of a Field Effect Transistors (FET) on paper substrates. The CNTs were dispersed in a water solution with sodium dodecyl sulphate (SDS) through ultrasonication, ultrasonic bath and a centrifugation to remove the supernatant and have a homogeneous solution. Several deposition tests were performed using different types of CNTs, dis-persants, papers substrates and deposition techniques, such as spray coating and inkjet printing. The characterization of CNTs was made by Scanning Electron Microscopy (SEM) and Hall Effect. The most suitable CNT coatings able to be used as semiconductor in FETs were deposited by spray coat-ing on a paper substrate with hydrophilic nanoporous surface (FS2) at 100 ºC, 4 bar, 10 cm height, 5 second of deposition time and 90 seconds of drying between steps (4 layers of CNTs were deposited). Planar electrolyte gated FETs were produced with these layers using gold-nickel gate, source and drain electrodes. Despite the small current modulation (Ion/Ioff ratio of 1.8) one of these devices have p-type conduction with a field effect mobility of 1.07 cm2/V.s.

Field-effect transistors based on Zinc oxide nanoparticles

This work reports the development of field-effect transistors (FETs), whose channel is based on zinc oxide (ZnO) nanoparticles (NPs). Using screen-printing as the primary deposition technique, different inks were developed, where the semiconducting ink is based on a ZnO NPs dispersion in ethyl cellulose (EC). These inks were used to print electrolyte-gated transistors (EGTs) in a staggered-top gate structure on glass substrates, using a lithium-based polymeric electrolyte. In another approach, FETs with a staggered-bottom gate structure on paper were developed using a sol-gel method to functionalize the paper’s surface with ZnO NPs, using zinc acetate dihydrate (ZnC4H6O4·2H2O) and sodium hydroxide (NaOH) as precursors. In this case, the paper itself was used as dielectric. The various layers of the two devices were characterized using X-ray diffraction (XRD), scanning electron microscopy (SEM), Fourier Transform Infrared spectroscopy (FTIR), thermogravimetric and differential scanning calorimetric analyses (TG-DSC). Electrochemical impedance spectroscopy (EIS) was used in order to evaluate the electric double-layer (EDL) formation, in the case of the EGTs. The ZnO NPs EGTs present electrical modulation for annealing temperatures equal or superior to 300 ºC and in terms of electrical properties they showed On/Off ratios in the order of 103, saturation mobilities (μSat) of 1.49x10-1 cm2(Vs)-1 and transconductance (gm) of 10-5 S. On the other hand, the ZnO NPs FETs on paper exhibited On/Off ratios in the order of 102, μSat of 4.83x10- 3 cm2(Vs)-1and gm around 10-8 S.

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW

Development of paper transistor with memory effect

This work will discuss the use of different paper membranes as both the substrate and dielectric for field-effect memory transistors. Three different nanofibrillated cellulose membranes (NFC) were used as the dielectric layer of the memory transistors (NFC), one with no additives, one with an added polymer PAE and one with added HCl. Gallium indium zinc oxide (GIZO) was used as the device’s semiconductor and gallium aluminium zinc oxide (GAZO) was used as the gate electrode. Fourier transform infrared spectroscopy (FTIR) was used to access the water content of the paper membranes before and after vacuum. It was found that the devices recovered their water too quickly for a difference to be noticeable in FTIR. The transistor’s electrical performance tests yielded a maximum ION/IOFF ratio of around 3,52x105 and a maximum subthreshold swing of 0,804 V/decade. The retention time of the dielectric charge that grants the transistor its memory capabilities was accessed by the measurement of the drain current periodically during 144 days. During this period the mean drain current did not lower, leaving the retention time of the device indeterminate. These results were compared with similar devices revealing these devices to be at the top tier of the state-of-the-art.

Análise do ciclo de vida do cimento. Caso de estudo: fábrica da Secil-Outão

O cimento é o material de construção mais utilizado na edificação de estruturas. A sua produção compreende um consumo material e energético muito significativo que se traduz numa contribuição igualmente relevante para a deterioração do ambiente. A presente dissertação consistiu na aplicação da abordagem de ciclo de vida ao processo de produção de dois tipos de cimento – CEM I 42,5 e CEM II 32,5 – com a finalidade de calcular o impacte ambiental de cada um e comprovar o desempenho ambiental superior do segundo. A análise do ciclo de vida foi desenvolvida de acordo com uma abordagem cradle-to-gate, segundo os requisitos das normas ISO 14040 e 14044 e da Norma Europeia 15804/2012. Os dados utilizados são específicos do processo de produção de cimento na fábrica de cimento Secil-Outão. Os resultados dos inventários do ciclo de vida demonstraram que, decorrente da utilização de uma maior quantidade de clínquer no seu fabrico, o CEM I 42,5 exige um maior consumo de matérias-primas naturais e de energia, tanto elétrica como térmica. O CEM II 32,5 apresenta consumos materiais e energéticos inferiores ao cimento do tipo I, devido a uma taxa de incorporação de clínquer mais baixa, mas compreende um consumo de matérias-primas secundárias mais alto. Em relação aos fluxos de saída, o CEM I 42,5 é responsável por níveis de emissão de CO2, PM10 e outros poluentes superiores aos do CEM II 32,5, em consequência do consumo elevado de combustíveis. A produção do cimento do tipo I é responsável por uma maior contribuição para a ecotoxicidade de sistemas marinhos e terrestres e para a deterioração da saúde pública, através da emissão de metais pesados, e para o agravamento das alterações climáticas, devido às emissões de CO2. A produção do cimento do tipo II apresenta um menor impacte ambiental e, por isso, um desempenho ambiental superior.

FPGA field oriented control of an axial flux motor-in-wheel

This paper presents the design and the prototype implementation of a three-phase power inverter developed to drive a motor-in-wheel. The control system is implemented in a FPGA (Field Programmable Gate Array) device. The paper describes the Field Oriented Control (FOC) algorithm and the Space Vector Modulation (SVM) technique that were implemented. The control platform uses a Spartan-3E FPGA board, programmed with Verilog language. Simulation and experimental results are presented to validate the developed system operation under different load conditions. Finally are presented conclusions based on the experimental results.