Discarge compilation from The Global River Discharge (RivDIS) Project

The Global River Discharge (RivDIS) data set contains monthly discharge measurements for 1018 stations located throughout the world. The period of record varies widely from station to station, with a mean of 21.5 years. These data were digitized from published UNESCO archives by Charles Voromarty, Balaze Fekete, and B.A. Tucker of the Complex Systems Research Center (CSRC) at the University of New Hampshire. River discharge is typically measured through the use of a rating curve that relates local water level height to discharge. This rating curve is used to estimate discharge from the observed water level. The rating curves are periodically rechecked and recalibrated through on-site measurement of discharge and river stage.

Towards the Compilation of a Consistent Asian International I-O Table--The Report of the General Survey on National I-O Tables--

This paper reports on the survey of the characteristic features of national input-output tables compiled by the member countries of the Asian International Input-Output Table project. In making any inter-regional tables, the presentation format of each constituent table has to be carefully studied in order to design a common adjustment rule. The survey was conducted in the period of 2003-04, with invaluable cooperation from each collaborating institution of the project. Some analytical findings are drawn from the survey results, such as the similarity between each national table and the Japanese table, the responsiveness to the 1993 SNA, and the major areas of conflict regarding the presentation format.

Compilation, application and challenge of IDE-JETRO's International Input-Output tables

International input-output tables are among the most useful tools for economic analysis. Since these tables provide detailed information about international production networks, they have recently attracted considerable attention in research on spatial economics, global value chains, and issues relating to trade in value-added. The Institute of Developing Economies at the Japan External Trade Organization (IDE-JETRO) has more than 40 years of experience in the construction and analysis of international input-output tables. This paper explains the development of IDE-JETRO’s multi-regional input-output projects including the construction of the Asian International Input-Output table and the Transnational Interregional Input-Output table between China and Japan. To help users understand the features of the tables, this paper also gives examples of their application.

Compilation of a regionally-extended inter-country input-output table and its application to global value chain analysis

Studies on the rise of global value chains (GVCs) have attracted a great deal of interest in the recent economics literature. However, due to statistical and methodological challenges, most existing research ignores domestic regional heterogeneity in assessing the impact of joining GVCs. GVCs are supported not only directly by domestic regions that export goods and services to the world market, but also indirectly by other domestic regions that provide parts, components, and intermediate services to final exporting regions. To better understand the nature of a country's position and degree of participation in GVCs, we need to fully examine the role of individual domestic regions. Understanding the domestic components of GVCs is especially important for larger economies such as China, the US, India and Japan, where there may be large variations in economic scale, geography of manufacturing, and development stages at the domestic regional level. This paper proposes a new framework for measuring domestic linkages to global value chains. This framework measures domestic linkages by endogenously embedding a target country's (e.g. China and Japan) domestic interregional input–output tables into the OECD inter-country input–output model. Using this framework, we can more clearly understand how global production is fragmented and extended internationally and domestically.

Optimizing Bottom Subcells for III-V-on-Si MultiJunction Solar Cells

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on silicon for photovoltaic applications. Such integration would offer a cost breakthrough for photovoltaic technology, unifying the low cost of silicon and the efficiency potential of III-V multijunction solar cells. In this study, we analyze several factors influencing the performance of the bottom subcell of this dual-junction, namely, 1) the formation of the emitter as a result of the phosphorus diffusion that takes place during the prenucleation temperature ramp and during the growth of the III-V layers; 2) the degradation in surface morphology during diffusion; and 3) the quality needed for the passivation provided by the GaP layer on the emitter.

Computational Schemes for Optimizing Domains of Attraction in Dynamical Systems

In this paper, several computational schemes are presented for the optimal tuning of the global behavior of nonlinear dynamical sys- tems. Specifically, the maximization of the size of domains of attraction associated with invariants in parametrized dynamical sys- tems is addressed. Cell Mapping (CM) tech- niques are used to estimate the size of the domains, and such size is then maximized via different optimization tools. First, a ge- netic algorithm is tested whose performance shows to be good for determining global maxima at the expense of high computa- tional cost. Secondly, an iterative scheme based on a Stochastic Approximation proce- dure (the Kiefer-Wolfowitz algorithm) is eval- uated showing acceptable performance at low cost. Finally, several schemes combining neu- ral network based estimations and optimiza- tion procedures are addressed with promising results. The performance of the methods is illus- trated with two applications: first on the well-known van der Pol equation with stan- dard parametrization, and second the tuning of a controller for saturated systems.

Optimizing the Density of Holes of EWT Solar Cells Taking Into Consideration Mechanical Aspects

EWT solar cells start from drilled wafers with approximately 100 holes/cm2. These holes act as stress concentrators leading to a reduction in the mechanical strength of this type of wafers. The viability of cells with higher density of holes has been studied. To this end, sets of wafers with different density of holes have been characterized. The ring on ring test has been employed and FE models have been developed to simulate the test. The statistical evaluation permits to draw conclusions about the reduction of the strength depending on the density of holes. Moreover, the stress concentration around the holes has been studied by means of the FE method employing the sub-modeling technique. The maximum principal stress of EWT wafers with twice the density of holes of commercial ones is almost the same. However, the mutual interaction between the stress concentration effects around neighboring holes is only observed for wafers with a density of 200 holes/cm2

Global flow analysis as a practical compilation tool

This paper addresses the issue of the practicality of global flow analysis in logic program compilation, in terms of speed of the analysis, precisión, and usefulness of the information obtained. To this end, design and implementation aspects are discussed for two practical abstract interpretation-based flow analysis systems: MA , the MCC And-parallel Analyzer and Annotator; and Ms, an experimental mode inference system developed for SB-Prolog. The paper also provides performance data obtained (rom these implementations and, as an example of an application, a study of the usefulness of the mode information obtained in reducing run-time checks in independent and-parallelism.Based on the results obtained, it is concluded that the overhead of global flow analysis is not prohibitive, while the results of analysis can be quite precise and useful.

Improving the compilation of prolog to C using moded types and determinism information

We describe the current status of and provide performance results for a prototype compiler of Prolog to C, ciaocc. ciaocc is novel in that it is designed to accept different kinds of high-level information, typically obtained via an automatic analysis of the initial Prolog program and expressed in a standardized language of assertions. This information is used to optimize the resulting C code, which is then processed by an off-the-shelf C compiler. The basic translation process essentially mimics the unfolding of a bytecode emulator with respect to the particular bytecode corresponding to the Prolog program. This is facilitated by a flexible design of the instructions and their lower-level components. This approach allows reusing a sizable amount of the machinery of the bytecode emulator: predicates already written in C, data definitions, memory management routines and áreas, etc., as well as mixing emulated bytecode with native code in a relatively straightforward way. We report on the performance of programs compiled by the current versión of the system, both with and without analysis information.

Improving the compilation of prolog to C using type and determinism information: Preliminary results

We describe the current status of and provide preliminary performance results for a compiler of Prolog to C. The compiler is novel in that it is designed to accept different kinds of high-level information (typically obtained via an analysis of the initial Prolog program and expressed in a standardized language of assertions) and use this information to optimize the resulting C code, which is then further processed by an off-the-shelf C compiler. The basic translation process used essentially mimics an unfolding of a C-coded bytecode emúlator with respect to the particular bytecode corresponding to the Prolog program. Optimizations are then applied to this unfolded program. This is facilitated by a more flexible design of the bytecode instructions and their lower-level components. This approach allows reusing a sizable amount of the machinery of the bytecode emulator: ancillary pieces of C code, data definitions, memory management routines and áreas, etc., as well as mixing bytecode emulated code with natively compiled code in a relatively straightforward way We report on the performance of programs compiled by the current versión of the system, both with and without analysis information.

An overview of ciao and its design philosophy

We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An important aspect of Ciao is that, in addition to supporting logic programming (and, in particular, Prolog), it provides the programmer with a large number of useful features from different programming paradigms and styles and that the use of each of these features (including those of Prolog) can be turned on and off at will for each program module. Thus, a given module may be using, e.g., higher order functions and constraints, while another module may be using assignment, predicates, Prolog meta-programming, and concurrency. Furthermore, the language is designed to be extensible in a simple and modular way. Another important aspect of Ciao is its programming environment, which provides a powerful preprocessor (with an associated assertion language) capable of statically finding non-trivial bugs, verifying that programs comply with specifications, and performing many types of optimizations (including automatic parallelization). Such optimizations produce code that is highly competitive with other dynamic languages or, with the (experimental) optimizing compiler, even that of static languages, all while retaining the flexibility and interactive development of a dynamic language. This compilation architecture supports modularity and separate compilation throughout. The environment also includes a powerful autodocumenter and a unit testing framework, both closely integrated with the assertion system. The paper provides an informal overview of the language and program development environment. It aims at illustrating the design philosophy rather than at being exhaustive, which would be impossible in a single journal paper, pointing instead to previous Ciao literature.