Multiple Input-Output Bidirectional Solid State Transformer Based on a Series Resonant Converter

Las fuentes de alimentación de modo conmutado (SMPS en sus siglas en inglés) se utilizan ampliamente en una gran variedad de aplicaciones. La tarea más difícil para los diseñadores de SMPS consiste en lograr simultáneamente la operación del convertidor con alto rendimiento y alta densidad de energía. El tamaño y el peso de un convertidor de potencia está dominado por los componentes pasivos, ya que estos elementos son normalmente más grandes y más pesados que otros elementos en el circuito. Para una potencia de salida dada, la cantidad de energía almacenada en el convertidor que ha de ser entregada a la carga en cada ciclo de conmutación, es inversamente proporcional a la frecuencia de conmutación del convertidor. Por lo tanto, el aumento de la frecuencia de conmutación se considera un medio para lograr soluciones más compactas con los niveles de densidad de potencia más altos. La importancia de investigar en el rango de alta frecuencia de conmutación radica en todos los beneficios que se pueden lograr: además de la reducción en el tamaño de los componentes pasivos, el aumento de la frecuencia de conmutación puede mejorar significativamente prestaciones dinámicas de convertidores de potencia. Almacenamiento de energía pequeña y el período de conmutación corto conducen a una respuesta transitoria del convertidor más rápida en presencia de las variaciones de la tensión de entrada o de la carga. Las limitaciones más importantes del incremento de la frecuencia de conmutación se relacionan con mayores pérdidas del núcleo magnético convencional, así como las pérdidas de los devanados debido a los efectos pelicular y proximidad. También, un problema potencial es el aumento de los efectos de los elementos parásitos de los componentes magnéticos - inductancia de dispersión y la capacidad entre los devanados - que causan pérdidas adicionales debido a las corrientes no deseadas. Otro factor limitante supone el incremento de las pérdidas de conmutación y el aumento de la influencia de los elementos parásitos (pistas de circuitos impresos, interconexiones y empaquetado) en el comportamiento del circuito. El uso de topologías resonantes puede abordar estos problemas mediante el uso de las técnicas de conmutaciones suaves para reducir las pérdidas de conmutación incorporando los parásitos en los elementos del circuito. Sin embargo, las mejoras de rendimiento se reducen significativamente debido a las corrientes circulantes cuando el convertidor opera fuera de las condiciones de funcionamiento nominales. A medida que la tensión de entrada o la carga cambian las corrientes circulantes incrementan en comparación con aquellos en condiciones de funcionamiento nominales. Se pueden obtener muchos beneficios potenciales de la operación de convertidores resonantes a más alta frecuencia si se emplean en aplicaciones con condiciones de tensión de entrada favorables como las que se encuentran en las arquitecturas de potencia distribuidas. La regulación de la carga y en particular la regulación de la tensión de entrada reducen tanto la densidad de potencia del convertidor como el rendimiento. Debido a la relativamente constante tensión de bus que se encuentra en arquitecturas de potencia distribuidas los convertidores resonantes son adecuados para el uso en convertidores de tipo bus (transformadores cc/cc de estado sólido). En el mercado ya están disponibles productos comerciales de transformadores cc/cc de dos puertos que tienen muy alta densidad de potencia y alto rendimiento se basan en convertidor resonante serie que opera justo en la frecuencia de resonancia y en el orden de los megahercios. Sin embargo, las mejoras futuras en el rendimiento de las arquitecturas de potencia se esperan que vengan del uso de dos o más buses de distribución de baja tensión en vez de una sola. Teniendo eso en cuenta, el objetivo principal de esta tesis es aplicar el concepto del convertidor resonante serie que funciona en su punto óptimo en un nuevo transformador cc/cc bidireccional de puertos múltiples para atender las necesidades futuras de las arquitecturas de potencia. El nuevo transformador cc/cc bidireccional de puertos múltiples se basa en la topología de convertidor resonante serie y reduce a sólo uno el número de componentes magnéticos. Conmutaciones suaves de los interruptores hacen que sea posible la operación en las altas frecuencias de conmutación para alcanzar altas densidades de potencia. Los problemas posibles con respecto a inductancias parásitas se eliminan, ya que se absorben en los Resumen elementos del circuito. El convertidor se caracteriza con una muy buena regulación de la carga propia y cruzada debido a sus pequeñas impedancias de salida intrínsecas. El transformador cc/cc de puertos múltiples opera a una frecuencia de conmutación fija y sin regulación de la tensión de entrada. En esta tesis se analiza de forma teórica y en profundidad el funcionamiento y el diseño de la topología y del transformador, modelándolos en detalle para poder optimizar su diseño. Los resultados experimentales obtenidos se corresponden con gran exactitud a aquellos proporcionados por los modelos. El efecto de los elementos parásitos son críticos y afectan a diferentes aspectos del convertidor, regulación de la tensión de salida, pérdidas de conducción, regulación cruzada, etc. También se obtienen los criterios de diseño para seleccionar los valores de los condensadores de resonancia para lograr diferentes objetivos de diseño, tales como pérdidas de conducción mínimas, la eliminación de la regulación cruzada o conmutación en apagado con corriente cero en plena carga de todos los puentes secundarios. Las conmutaciones en encendido con tensión cero en todos los interruptores se consiguen ajustando el entrehierro para obtener una inductancia magnetizante finita en el transformador. Se propone, además, un cambio en los señales de disparo para conseguir que la operación con conmutaciones en apagado con corriente cero de todos los puentes secundarios sea independiente de la variación de la carga y de las tolerancias de los condensadores resonantes. La viabilidad de la topología propuesta se verifica a través una extensa tarea de simulación y el trabajo experimental. La optimización del diseño del transformador de alta frecuencia también se aborda en este trabajo, ya que es el componente más voluminoso en el convertidor. El impacto de de la duración del tiempo muerto y el tamaño del entrehierro en el rendimiento del convertidor se analizan en un ejemplo de diseño de transformador cc/cc de tres puertos y cientos de vatios de potencia. En la parte final de esta investigación se considera la implementación y el análisis de las prestaciones de un transformador cc/cc de cuatro puertos para una aplicación de muy baja tensión y de decenas de vatios de potencia, y sin requisitos de aislamiento. Abstract Recently, switch mode power supplies (SMPS) have been used in a great variety of applications. The most challenging issue for designers of SMPS is to achieve simultaneously high efficiency operation at high power density. The size and weight of a power converter is dominated by the passive components since these elements are normally larger and heavier than other elements in the circuit. If the output power is constant, the stored amount of energy in the converter which is to be delivered to the load in each switching cycle is inversely proportional to the converter’s switching frequency. Therefore, increasing the switching frequency is considered a mean to achieve more compact solutions at higher power density levels. The importance of investigation in high switching frequency range comes from all the benefits that can be achieved. Besides the reduction in size of passive components, increasing switching frequency can significantly improve dynamic performances of power converters. Small energy storage and short switching period lead to faster transient response of the converter against the input voltage and load variations. The most important limitations for pushing up the switching frequency are related to increased conventional magnetic core loss as well as the winding loss due to the skin and proximity effect. A potential problem is also increased magnetic parasitics – leakage inductance and capacitance between the windings – that cause additional loss due to unwanted currents. Higher switching loss and the increased influence of printed circuit boards, interconnections and packaging on circuit behavior is another limiting factor. Resonant power conversion can address these problems by using soft switching techniques to reduce switching loss incorporating the parasitics into the circuit elements. However the performance gains are significantly reduced due to the circulating currents when the converter operates out of the nominal operating conditions. As the input voltage or the load change the circulating currents become higher comparing to those ones at nominal operating conditions. Multiple Input-Output Many potential gains from operating resonant converters at higher switching frequency can be obtained if they are employed in applications with favorable input voltage conditions such as those found in distributed power architectures. Load and particularly input voltage regulation reduce a converter’s power density and efficiency. Due to a relatively constant bus voltage in distributed power architectures the resonant converters are suitable for bus voltage conversion (dc/dc or solid state transformation). Unregulated two port dc/dc transformer products achieving very high power density and efficiency figures are based on series resonant converter operating just at the resonant frequency and operating in the megahertz range are already available in the market. However, further efficiency improvements of power architectures are expected to come from using two or more separate low voltage distribution buses instead of a single one. The principal objective of this dissertation is to implement the concept of the series resonant converter operating at its optimum point into a novel bidirectional multiple port dc/dc transformer to address the future needs of power architectures. The new multiple port dc/dc transformer is based on a series resonant converter topology and reduces to only one the number of magnetic components. Soft switching commutations make possible high switching frequencies to be adopted and high power densities to be achieved. Possible problems regarding stray inductances are eliminated since they are absorbed into the circuit elements. The converter features very good inherent load and cross regulation due to the small output impedances. The proposed multiple port dc/dc transformer operates at fixed switching frequency without line regulation. Extensive theoretical analysis of the topology and modeling in details are provided in order to compare with the experimental results. The relationships that show how the output voltage regulation and conduction losses are affected by the circuit parasitics are derived. The methods to select the resonant capacitor values to achieve different design goals such as minimum conduction losses, elimination of cross regulation or ZCS operation at full load of all the secondary side bridges are discussed. ZVS turn-on of all the switches is achieved by relying on the finite magnetizing inductance of the Abstract transformer. A change of the driving pattern is proposed to achieve ZCS operation of all the secondary side bridges independent on load variations or resonant capacitor tolerances. The feasibility of the proposed topology is verified through extensive simulation and experimental work. The optimization of the high frequency transformer design is also addressed in this work since it is the most bulky component in the converter. The impact of dead time interval and the gap size on the overall converter efficiency is analyzed on the design example of the three port dc/dc transformer of several hundreds of watts of the output power for high voltage applications. The final part of this research considers the implementation and performance analysis of the four port dc/dc transformer in a low voltage application of tens of watts of the output power and without isolation requirements.

Electrochemical potentials (Quasi-Fermi Levels) and the operation of hot-carrier, impact-ionization, and intermediate-band solar cells

In the framework of the so-called third generation solar cells, three main concepts have been proposed in order to exceed the limiting efficiency of single-gap solar cells: the hot-carrier solar cell, the impact-ionization or multiple-exciton-generation solar cell, and the intermediate-band solar cell. At first sight, the three concepts are different, but in this paper, we illustrate how all these concepts, including the single-gap solar cell, share a common trunk that we call "core photovoltaic material." We demonstrate that each one of these next-generation concepts differentiates in fact from this trunk depending on the hypotheses that are made about the physical principles governing the electron electrochemical potentials. In the process, we also clarify the differences between electron, phonon, and photon chemical potentials (the three fundamental particles involved in the operation of the solar cell). The in-depth discussion of the physics involved about the operation of these cells also provides new insights about the operation of these cells.

Analysis of Contributions to NO2 Ambient Air Quality Levels in Madrid City (Spain) through Modeling. Implications for the Development of Policies and Air Quality Monitoring

As environmental standards become more stringent (e.g. European Directive 2008/50/EC), more reliable and sophisticated modeling tools are needed to simulate measures and plans that may effectively tackle air quality exceedances, common in large cities across Europe, particularly for NO2. Modeling air quality in urban areas is rather complex since observed concentration values are a consequence of the interaction of multiple sources and processes that involve a wide range of spatial and temporal scales. Besides a consistent and robust multi-scale modeling system, comprehensive and flexible emission inventories are needed. This paper discusses the application of the WRF-SMOKE-CMAQ system to the Madrid city (Spain) to assess the contribution of the main emitting sectors in the region. A detailed emission inventory was compiled for this purpose. This inventory relies on bottom-up methods for the most important sources. It is coupled with the regional traffic model and it makes use of an extensive database of industrial, commercial and residential combustion plants. Less relevant sources are downscaled from national or regional inventories. This paper reports the methodology and main results of the source apportionment study performed to understand the origin of pollution (main sectors and geographical areas) and define clear targets for the abatement strategy. Finally the structure of the air quality monitoring is analyzed and discussed to identify options to improve the monitoring strategy not only in the Madrid city but the whole metropolitan area.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Multiple Robots, Single Operator: Considerations About Information And Commanding

Multiple robot, single operator scenarios suppose a challenge in terms of human factors. Two relevant issues are keeping the situational awareness and managing the workload of operators. In order to address these problems, this work analyses the management of information and commands in multi-robot missions. About the information, this paper proposes a selection based on mission and operator states. Regarding the commands, this work reflects about the levels of automation and the methods of commanding.

The drug efflux protein, P-glycoprotein, additionally protects drug-resistant tumor cells from multiple forms of caspase-dependent apoptosis

Multidrug resistance mediated by the drug efflux protein, P-glycoprotein (P-gp), is one mechanism that tumor cells use to escape death induced by chemotherapeutic agents. However, the mechanism by which P-gp confers resistance to a large variety of structurally diverse molecules has remained elusive. In this study, classical multidrug resistant human CEM and K562 tumor cell lines expressing high levels of P-gp were less sensitive to multiple forms of caspase-dependent cell death, including that mediated by cytotoxic drugs and ligation of Fas. The DNA fragmentation and membrane damage inflicted by these stimuli were defined as caspase dependent by various soluble peptide fluoromethylketone caspase inhibitors. Inhibition of P-gp function by the anti-P-gp mAb MRK-16 or verapamil could reverse resistance to these forms of cell death. Inhibition of P-gp function also enhanced drug or Fas-mediated activation of caspase-3 in drug-resistant CEM cells. By contrast, caspase-independent cell death events in the same cells, including those mediated by pore-forming proteins or intact NK cells, were not affected by P-gp expression. These observations suggest that, in addition to effluxing drugs, P-gp may play a specific role in regulating some caspase-dependent apoptotic pathways.

BAS1: A gene regulating brassinosteroid levels and light responsiveness in Arabidopsis

The Arabidopsis bas1-D mutation suppresses the long hypocotyl phenotype caused by mutations in the photoreceptor phytochrome B (phyB). The adult phenotype of bas1-D phyB-4 double mutants mimics that of brassinosteroid biosynthetic and response mutants. bas1-D phyB-4 has reduced levels of brassinosteroids and accumulates 26-hydroxybrassinolide in feeding experiments. The basis for the mutant phenotype is the enhanced expression of a cytochrome P450 (CYP72B1). bas1-D suppresses a phyB-null allele, but not a phyA-null mutation, and partially suppresses a cryptochrome-null mutation. Seedlings with reduced BAS1 expression are hyperresponsive to brassinosteroids in a light-dependent manner and display reduced sensitivity to light under a variety of conditions. Thus, BAS1 represents one of the control points between multiple photoreceptor systems and brassinosteroid signal transduction.

Membrane-anchored Plakoglobins Have Multiple Mechanisms of Action in Wnt Signaling

In Wnt signaling, β-catenin and plakoglobin transduce signals to the nucleus through interactions with TCF-type transcription factors. However, when plakoglobin is artificially engineered to restrict it to the cytoplasm by fusion with the transmembrane domain of connexin (cnxPg), it efficiently induces a Wnt-like axis duplication phenotype in Xenopus. In Xenopus embryos, maternal XTCF3 normally represses ventral expression of the dorsalizing gene Siamois. Two models have been proposed to explain the Wnt-like activity of cnxPg: 1) that cnxPg inhibits the machinery involved in the turnover of cytosolic β-catenin, which then accumulates and inhibits maternal XTCF3, and 2) that cnxPg directly acts to inhibit XTCF3 activity. To distinguish between these models, we created a series of N-terminal deletion mutations of cnxPg and examined their ability to induce an ectopic axis in Xenopus, activate a TCF-responsive reporter (OT), stabilize β-catenin, and colocalize with components of the Wnt signaling pathway. cnxPg does not colocalize with the Wnt pathway component Dishevelled, but it does lead to the redistribution of APC and Axin, two proteins involved in the regulation of β-catenin turnover. Expression of cnxPg increases levels of cytosolic β-catenin; however, this effect does not completely explain its signaling activity. Although cnxPg and Wnt-1 stabilize β-catenin to similar extents, cnxPg activates OT to 10- to 20-fold higher levels than Wnt-1. Moreover, although LEF1 and TCF4 synergize with β-catenin and plakoglobin to activate OT, both suppress the signaling activity of cnxPg. In contrast, XTCF3 suppresses the signaling activity of both β-catenin and cnxPg. Both exogenous XLEF1 and XTCF3 are sequestered in the cytoplasm of Xenopus cells by cnxPg. Based on these data, we conclude that, in addition to its effects on β-catenin, cnxPg interacts with other components of the Wnt pathway, perhaps TCFs, and that these interactions contribute to its signaling activity.

Dynamic expression of multiple scavenger receptor cysteine-rich genes in coelomocytes of the purple sea urchin

Coelomocytes, the heterogeneous population of sea urchin putative immune cells, were found to express a complex set of transcripts featuring scavenger receptor cysteine-rich (SRCR) repeats. SRCR domains define a metazoan superfamily of proteins, many of which are implicated in development and regulation of the immune system of vertebrates. Coelomocytes transcribe multiple SRCR genes from among a multigene family encoding an estimated number of 1,200 SRCR domains in specific patterns particular to each individual. Transcription levels for given SRCR genes may range from pronounced to undetectable, yet all tested animals harbor the genomic loci encoding these genes. Analysis of several SRCR genes revealed multiple loci corresponding to each type. In the case of one SRCR type, a cluster of at least three genes was detected within a 133-kb bacterial artificial chromosome insert, and conserved as well as unique regions were identified in sequences of three genomic clones derived from a single animal. Array hybridizations with repeated samples of coelomocyte messages revealed substantial alterations in levels of expression of many SRCR genes, with fluctuations of up to 10-fold in 1 week and up to 30-fold over a period of 3 months. This report is the first demonstration of genomic and transcriptional complexity in molecules expressed by invertebrate coelomocytes. The mechanisms controlling SRCR gene expression and the functional significance of this dynamic system await elucidation.

Adeno-associated viral vector-mediated gene transfer results in long-term enzymatic and functional correction in multiple organs of Fabry mice

Fabry disease is a lysosomal storage disorder caused by a deficiency of the lysosomal enzyme α-galactosidase A (α-gal A). This enzyme deficiency leads to impaired catabolism of α-galactosyl-terminal lipids such as globotriaosylceramide (Gb3). Patients develop painful neuropathy and vascular occlusions that progressively lead to cardiovascular, cerebrovascular, and renal dysfunction and early death. Although enzyme replacement therapy and bone marrow transplantation have shown promise in the murine analog of Fabry disease, gene therapy holds a strong potential for treating this disease in humans. Delivery of the normal α-gal A gene (cDNA) into a depot organ such as liver may be sufficient to elicit corrective circulating levels of the deficient enzyme. To investigate this possibility, a recombinant adeno-associated viral vector encoding human α-gal A (rAAV-AGA) was constructed and injected into the hepatic portal vein of Fabry mice. Two weeks postinjection, α-gal A activity in the livers of rAAV-AGA-injected Fabry mice was 20–35% of that of the normal mice. The transduced animals continued to show higher α-gal A levels in liver and other tissues compared with the untouched Fabry controls as long as 6 months after treatment. In parallel to the elevated enzyme levels, we see significant reductions in Gb3 levels to near normal at 2 and 5 weeks posttreatment. The lower Gb3 levels continued in liver, spleen, and heart, up to 25 weeks with no significant immune response to the virus or α-gal A. Also, no signs of liver toxicity occurred after the rAAV-AGA administration. These findings suggest that an AAV-mediated gene transfer may be useful for the treatment of Fabry disease and possibly other metabolic disorders.

Myosin light chain kinase (MLCK) gene disruption in Dictyostelium: a role for MLCK-A in cytokinesis and evidence for multiple MLCKs.

We have created a strain of Dictyostelium that is deficient for the Ca2+/calmodulin-independent MLCK-A. This strain undergoes cytokinesis less efficiently than wild type, which results in an increased frequency of multinucleate cells when grown in suspension. The MLCK-A-cells are able, however, to undergo development and to cap crosslinked surface receptors, processes that require myosin heavy chain. Phosphorylated regulatory light chain (RLC) is still present in MLCK-A-cells, indicating that Dictyostelium has one or more additional protein kinases capable of phosphorylating RLC. Concanavalin A treatment was found to induce phosphorylation of essentially all of the RLC in wild-type cells, but RLC phosphorylation levels in MLCK-A-cells are unaffected by concanavalin A. Thus MLCK-A is regulated separately from the other MLCK(s) in the cell.

Increased mRNA levels for components of the lysosomal, Ca2+-activated, and ATP-ubiquitin-dependent proteolytic pathways in skeletal muscle from head trauma patients.

The cellular mechanisms responsible for enhanced muscle protein breakdown in hospitalized patients, which frequently results in lean body wasting, are unknown. To determine whether the lysosomal, Ca2+-activated, and ubiquitin-proteasome proteolytic pathways are activated, we measured mRNA levels for components of these processes in muscle biopsies from severe head trauma patients. These patients exhibited negative nitrogen balance and increased rates of whole-body protein breakdown (assessed by [13C]leucine infusion) and of myofibrillar protein breakdown (assessed by 3-methylhistidine urinary excretion). Increased muscle mRNA levels for cathepsin D, m-calpain, and critical components of the ubiquitin proteolytic pathway (i.e., ubiquitin, the 14-kDa ubiquitin-conjugating enzyme E2, and proteasome subunits) paralleled these metabolic adaptations. The data clearly support a role for multiple proteolytic processes in increased muscle proteolysis. The ubiquitin proteolytic pathway could be activated by altered glucocorticoid production and/or increased circulating levels of interleukin 1beta and interleukin 6 observed in head trauma patients and account for the breakdown of myofibrillar proteins, as was recently reported in animal studies.

Embryonic stem cells express multiple Eph-subfamily receptor tyrosine kinases.

Eph and its homologues form the largest subfamily of receptor tyrosine kinases. Normal expression patterns of this subfamily indicate roles in differentiation and development, whereas their overexpression has been linked to oncogenesis. This study investigated the potential role of Eph-related molecules during very early embryonic development by examining their expression in embryonic stem (ES) cells and embryoid bodies differentiated from ES cells in vitro. By use of a strategy based on reverse transcriptase-mediated PCR, nine clones containing Eph-subfamily sequence were isolated from ES cells. Of these, eight were almost identical to one of four previously identified molecules (Sek, Nuk, Eck, and Mek4). However, one clone contained sequence from a novel Eph-subfamily member, which was termed embryonic stem-cell kinase or Esk. Northern analysis showed expression of Esk in ES cells, embryoid bodies, day 12 mouse embryos, and some tissues of the adult animal. Levels of expression were similar in ES cells and embryoid bodies. By comparison, Mek4 showed no significant transcription in the ES cell cultures by Northern analysis, whereas Eck displayed stronger signals in ES cells than in the embryoid bodies. These results suggest that Eph-subfamily molecules may play roles during the earliest phases of embryogenesis. Furthermore, the relative importance of different members of this subfamily appears to change as development proceeds.

Activation of the inducible form of nitric oxide synthase in the brains of patients with multiple sclerosis.

Nitric oxide (NO) has been implicated as a pathogenic mediator in a variety of central nervous system (CNS) disease states, including the animal model of multiple sclerosis (MS) and experimental allergic encephalomyelitis. We have examined post-mortem brain tissues collected from patients previously diagnosed with MS, as well as tissues collected from the brains of patients dying without neuropathies. Both Northern blot analysis and reverse transcriptase (RT)-driven in situ PCR (RT-in situ PCR) studies demonstrated that inducible NO synthase (iNOS) mRNA was present in the brain tissues from MS patients but was absent in equivalent tissues from normal controls. We have also performed experiments identifying the cell type responsible for iNOS expression by RT-in situ PCR in combination with immunohistochemistry. Concomitantly, we analyzed the tissues for the presence of the NO reaction product nitrotyrosine to demonstrate the presence of a protein nitrosylation adduct. We report here that iNOS mRNA was detectable in the brains of 100% of the CNS tissues from seven MS patients examined but in none of the three normal brains. RT-in situ PCR experiments also demonstrated the presence of iNOS mRNA in the cytoplasm of cells that also expressed the ligand recognized by the Ricinus communis agglutinin 1 (RCA-1), a monocyte/macrophage lineage marker. Additionally, specific labeling of cells was observed when brain tissues from MS patients were exposed to antisera reactive with nitrotyrosine residues but was significantly less plentiful in brain tissue from patients without CNS disease. These results demonstrate that iNOS, one of the enzymes responsible for the production of NO, is expressed at significant levels in the brains of patients with MS and may contribute to the pathology associated with the disease.

Potentiation of epidermal growth factor receptor-mediated oncogenesis by c-Src: implications for the etiology of multiple human cancers.

c-Src is a nontransforming tyrosine kinase that participates in signaling events mediated by a variety of polypeptide growth factor receptors, including the epidermal growth factor receptor (EGFR). Overexpression and continual ligand stimulation of the EGFR results in morphological transformation of cells in vitro and tumor development in vivo. Elevated levels of c-Src and the EGFR are found in a variety of human malignancies, raising the question of whether c-Src can functionally cooperate with the EGFR during tumorigenesis. To address this issue, we generated c-Src/EGFR double overexpressors and compared their proliferative and biochemical characteristics to those of single overexpressors and control cells. We found that in cells expressing high levels of receptor, c-Src potentiated DNA synthesis, growth in soft agar, and tumor formation in nude mice. Growth potentiation was associated with the formation of a heterocomplex between c-Src and activated EGFR, the appearance of a distinct tyrosyl phosphorylation on the receptor, and an enhancement of receptor substrate phosphorylation. These findings indicate that c-Src is capable of potentiating receptor-mediated tumorigenesis and suggest that synergism between c-Src and the EGFR may contribute to a more aggressive phenotype in multiple human tumors.