On the Condition Monitoring of Induction machines

The research of condition monitoring of electric motors has been wide for several decades. The research and development at universities and in industry has provided means for the predictive condition monitoring. Many different devices and systems are developed and are widely used in industry, transportation and in civil engineering. In addition, many methods are developed and reported in scientific arenas in order to improve existing methods for the automatic analysis of faults. The methods, however, are not widely used as a part of condition monitoring systems. The main reasons are, firstly, that many methods are presented in scientific papers but their performance in different conditions is not evaluated, secondly, the methods include parameters that are so case specific that the implementation of a systemusing such methods would be far from straightforward. In this thesis, some of these methods are evaluated theoretically and tested with simulations and with a drive in a laboratory. A new automatic analysis method for the bearing fault detection is introduced. In the first part of this work the generation of the bearing fault originating signal is explained and its influence into the stator current is concerned with qualitative and quantitative estimation. The verification of the feasibility of the stator current measurement as a bearing fault indicatoris experimentally tested with the running 15 kW induction motor. The second part of this work concentrates on the bearing fault analysis using the vibration measurement signal. The performance of the micromachined silicon accelerometer chip in conjunction with the envelope spectrum analysis of the cyclic bearing faultis experimentally tested. Furthermore, different methods for the creation of feature extractors for the bearing fault classification are researched and an automatic fault classifier using multivariate statistical discrimination and fuzzy logic is introduced. It is often important that the on-line condition monitoring system is integrated with the industrial communications infrastructure. Two types of a sensor solutions are tested in the thesis: the first one is a sensor withcalculation capacity for example for the production of the envelope spectra; the other one can collect the measurement data in memory and another device can read the data via field bus. The data communications requirements highly depend onthe type of the sensor solution selected. If the data is already analysed in the sensor the data communications are needed only for the results but in the other case, all measurement data need to be transferred. The complexity of the classification method can be great if the data is analysed at the management level computer, but if the analysis is made in sensor itself, the analyses must be simple due to the restricted calculation and memory capacity.

Security in RFID devices

Aquest projecte inclou una aproximació als conceptes de RFID i targetes contactless centrant-se en l’ampliament usat MIFARE Classic chip. L’objectiu principal es mostrar el seu funcionament i les seves vulnerabilitats, així com alguns exemples pràctics fent una anàlisi de diferents serveis que les utilitzen.

The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

Oikosulkumoottorin roottorivaurioiden tunnistaminen staattorivirran avulla

Diplomityössä esitellään menetelmiä sauvarikon toteamiseksi. Työn tarkoituksena on tutkia roottorivaurioita staattorivirran avulla. Työ jaetaan karkeasti kolmeen osa-alueeseen: oikosulkumoottorin vikoihin, roottorivaurioiden tunnistamiseen ja signaalinkäsittelymenetelmiin, jonka avulla havaitaan sauvarikko. Oikosulkumoottorin vikoja ovat staattorikäämien vauriot ja roottorivauriot. Roottorikäämien vaurioita ovat roottori sauvojen murtuminen sekä roottorisauvan irtoaminen oikosulkujenkaan päästä. Roottorivaurioiden tunnistamismenetelmiä ovat parametrin arviointi ja virtaspektrianalyysi. Työn alkuosassa esitellään oikosulkumoottorien rakenne ja toiminta. Esitellään moottoriin kohdistuvia vikoja ja etsitään ratkaisumenetelmiä roottorivaurioiden tunnistamisessa. Lopuksi tutkitaan, kuinka staattorimittaustietojen perusteella saadut tulokset voidaan käsitellä FFT -algoritmilla ja kuinka FFT -algoritmi voidaan toteuttaa sulautettuna Sharc -prosessorin avulla. Työssä käytetään ADSP 21062 EZ -LAB kehitysympäristöä, jonka avulla voidaan ajaa ohjelmia RAM-sirusta, joka on vuorovaikutuksessa SHARC -laudassa oleviin laitteisiin.

The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custombuilt optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.

Open Device Lab: movement to improve web and app experience

We present here the first part of the literature review regarding our study object, the Open Device Labs. The research on ODLs emerges from the observation of worldwide non-profit movement, which, through mutual collaboration, information and devices sharing, proposes a final improvement on user’s experience with the web and app.

Real-time Musical Pair Improvisation on Mobile Devices

This thesis discusses the design and implementation of a real-time musical pair improvisation scenario for mobile devices. In the scenario transferring musical information over a network connection was required. The suitability of available wireless communication technologies was evaluated and communication was analyzed and designed on multiple layers of TCP/IP protocol stack. Also an application layer protocol was designed and implemented for the scenario. The implementation was integrated into a mobile musical software for children using available software components and libraries although the used platform lead to hardware and software constraints. Software limitations were taken into account in design. The results show that real-time musical improvisation can be implemented with wireless communication and mobile technology. The results also show that link layer had the most significant effect on real-time communication in the scenario.

On the potential utilisation of sawdust and wood chip screenings

This work is based on the utilisation of sawdust and wood chip screenings for different purposes. A substantial amount of these byproducts are readily available in the Finnish forest industry. A black liquor impregnation study showed that sawdust-like wood material behaves differently from normal chips. Furthermore, the fractionation and removal of the smallest size fractions did not have a significant effect on the impregnation of sawdust-like wood material. Sawdust kraft cooking equipped with an impregnation stage increases the cooking yield and decreases the lignin content of the produced pulp. Impregnation also increases viscosity of the pulp and decreases chlorine dioxide consumption in bleaching. In addition, impregnation increases certain pulp properties after refining. Hydrotropic extraction showed that more lignin can be extracted from hardwood than softwood. However, the particle size had a major influence on the lignin extraction. It was possible to extract more lignin from spruce sawdust than spruce chips. Wood chip screenings are usually combusted to generate energy. They can also be used in the production of kraft pulp, ethanol and chemicals. It is not economical to produce ethanol from wood chip screenings because of the expensive wood material. Instead, they should be used for production of steam and energy, kraft pulp and higher value added chemicals. Bleached sawdust kraft pulp can be used to replace softwood kraft pulp in mechanical pulp based papers because it can improve certain physical properties. It is economically more feasible to use bleached sawdust kraft pulp in stead of softwood kraft pulp, especially when the reinforcement power requirement is moderate.

The Usage of Microsoft Push Notification Service on Mobile Devices

Along with the increasing in demand of mobile computing, Push Notification (PN) is widely used in mobile phones and other devices. PN allows the developer to send messages to the end users even when the client application is not running at the moment. This solves the problem produced by non-supported multi-tasking feature as well as saving battery life. Microsoft Push Notification Service (MPNS) is one solution to use PNs in Windows Phones. The thesis gives the developers an idea of how to use PNs by introducing MPNS, comparing MPNS with other Push Notification Services, usage of different PN types analysis, and PN simulation system implementation.

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.

On Dynamic Monitoring Methods for Networks-on-Chip

Rapid ongoing evolution of multiprocessors will lead to systems with hundreds of processing cores integrated in a single chip. An emerging challenge is the implementation of reliable and efficient interconnection between these cores as well as other components in the systems. Network-on-Chip is an interconnection approach which is intended to solve the performance bottleneck caused by traditional, poorly scalable communication structures such as buses. However, a large on-chip network involves issues related to congestion problems and system control, for instance. Additionally, faults can cause problems in multiprocessor systems. These faults can be transient faults, permanent manufacturing faults, or they can appear due to aging. To solve the emerging traffic management, controllability issues and to maintain system operation regardless of faults a monitoring system is needed. The monitoring system should be dynamically applicable to various purposes and it should fully cover the system under observation. In a large multiprocessor the distances between components can be relatively long. Therefore, the system should be designed so that the amount of energy-inefficient long-distance communication is minimized. This thesis presents a dynamically clustered distributed monitoring structure. The monitoring is distributed so that no centralized control is required for basic tasks such as traffic management and task mapping. To enable extensive analysis of different Network-on-Chip architectures, an in-house SystemC based simulation environment was implemented. It allows transaction level analysis without time consuming circuit level implementations during early design phases of novel architectures and features. The presented analysis shows that the dynamically clustered monitoring structure can be efficiently utilized for traffic management in faulty and congested Network-on-Chip-based multiprocessor systems. The monitoring structure can be also successfully applied for task mapping purposes. Furthermore, the analysis shows that the presented in-house simulation environment is flexible and practical tool for extensive Network-on-Chip architecture analysis.

Power cycling lifetime estimation of IGBT power modules based on chip temperature modeling

In this doctoral thesis, methods to estimate the expected power cycling life of power semiconductor modules based on chip temperature modeling are developed. Frequency converters operate under dynamic loads in most electric drives. The varying loads cause thermal expansion and contraction, which stresses the internal boundaries between the material layers in the power module. Eventually, the stress wears out the semiconductor modules. The wear-out cannot be detected by traditional temperature or current measurements inside the frequency converter. Therefore, it is important to develop a method to predict the end of the converter lifetime. The thesis concentrates on power-cycling-related failures of insulated gate bipolar transistors. Two types of power modules are discussed: a direct bonded copper (DBC) sandwich structure with and without a baseplate. Most common failure mechanisms are reviewed, and methods to improve the power cycling lifetime of the power modules are presented. Power cycling curves are determined for a module with a lead-free solder by accelerated power cycling tests. A lifetime model is selected and the parameters are updated based on the power cycling test results. According to the measurements, the factor of improvement in the power cycling lifetime of modern IGBT power modules is greater than 10 during the last decade. Also, it is noticed that a 10 C increase in the chip temperature cycle amplitude decreases the lifetime by 40%. A thermal model for the chip temperature estimation is developed. The model is based on power loss estimation of the chip from the output current of the frequency converter. The model is verified with a purpose-built test equipment, which allows simultaneous measurement and simulation of the chip temperature with an arbitrary load waveform. The measurement system is shown to be convenient for studying the thermal behavior of the chip. It is found that the thermal model has a 5 C accuracy in the temperature estimation. The temperature cycles that the power semiconductor chip has experienced are counted by the rainflow algorithm. The counted cycles are compared with the experimentally verified power cycling curves to estimate the life consumption based on the mission profile of the drive. The methods are validated by the lifetime estimation of a power module in a direct-driven wind turbine. The estimated lifetime of the IGBT power module in a direct-driven wind turbine is 15 000 years, if the turbine is located in south-eastern Finland.