Thermal, stress, and traps effects in AlGaN/GaN HEMTs

GaN y AlN son materiales semiconductores piezoeléctricos del grupo III-V. La heterounión AlGaN/GaN presenta una elevada carga de polarización tanto piezoeléctrica como espontánea en la intercara, lo que genera en su cercanía un 2DEG de grandes concentración y movilidad. Este 2DEG produce una muy alta potencia de salida, que a su vez genera una elevada temperatura de red. Las tensiones de puerta y drenador provocan un stress piezoeléctrico inverso, que puede afectar a la carga de polarización piezoeléctrica y así influir la densidad 2DEG y las características de salida. Por tanto, la física del dispositivo es relevante para todos sus aspectos eléctricos, térmicos y mecánicos. En esta tesis se utiliza el software comercial COMSOL, basado en el método de elementos finitos (FEM), para simular el comportamiento integral electro-térmico, electro-mecánico y electro-térmico-mecánico de los HEMTs de GaN. Las partes de acoplamiento incluyen el modelo de deriva y difusión para el transporte electrónico, la conducción térmica y el efecto piezoeléctrico. Mediante simulaciones y algunas caracterizaciones experimentales de los dispositivos, hemos analizado los efectos térmicos, de deformación y de trampas. Se ha estudiado el impacto de la geometría del dispositivo en su auto-calentamiento mediante simulaciones electro-térmicas y algunas caracterizaciones eléctricas. Entre los resultados más sobresalientes, encontramos que para la misma potencia de salida la distancia entre los contactos de puerta y drenador influye en generación de calor en el canal, y así en su temperatura. El diamante posee une elevada conductividad térmica. Integrando el diamante en el dispositivo se puede dispersar el calor producido y así reducir el auto-calentamiento, al respecto de lo cual se han realizado diversas simulaciones electro-térmicas. Si la integración del diamante es en la parte superior del transistor, los factores determinantes para la capacidad disipadora son el espesor de la capa de diamante, su conductividad térmica y su distancia a la fuente de calor. Este procedimiento de disipación superior también puede reducir el impacto de la barrera térmica de intercara entre la capa adaptadora (buffer) y el substrato. La muy reducida conductividad eléctrica del diamante permite que pueda contactar directamente el metal de puerta (muy cercano a la fuente de calor), lo que resulta muy conveniente para reducir el auto-calentamiento del dispositivo con polarización pulsada. Por otra parte se simuló el dispositivo con diamante depositado en surcos atacados sobre el sustrato como caminos de disipación de calor (disipador posterior). Aquí aparece una competencia de factores que influyen en la capacidad de disipación, a saber, el surco atacado contribuye a aumentar la temperatura del dispositivo debido al pequeño tamaño del disipador, mientras que el diamante disminuiría esa temperatura gracias a su elevada conductividad térmica. Por tanto, se precisan capas de diamante relativamente gruesas para reducer ele efecto de auto-calentamiento. Se comparó la simulación de la deformación local en el borde de la puerta del lado cercano al drenador con estructuras de puerta estándar y con field plate, que podrían ser muy relevantes respecto a fallos mecánicos del dispositivo. Otras simulaciones se enfocaron al efecto de la deformación intrínseca de la capa de diamante en el comportamiento eléctrico del dispositivo. Se han comparado los resultados de las simulaciones de la deformación y las características eléctricas de salida con datos experimentales obtenidos por espectroscopía micro-Raman y medidas eléctricas, respectivamente. Los resultados muestran el stress intrínseco en la capa producido por la distribución no uniforme del 2DEG en el canal y la región de acceso. Además de aumentar la potencia de salida del dispositivo, la deformación intrínseca en la capa de diamante podría mejorar la fiabilidad del dispositivo modulando la deformación local en el borde de la puerta del lado del drenador. Finalmente, también se han simulado en este trabajo los efectos de trampas localizados en la superficie, el buffer y la barrera. Las medidas pulsadas muestran que tanto las puertas largas como las grandes separaciones entre los contactos de puerta y drenador aumentan el cociente entre la corriente pulsada frente a la corriente continua (lag ratio), es decir, disminuir el colapse de corriente (current collapse). Este efecto ha sido explicado mediante las simulaciones de los efectos de trampa de superficie. Por su parte, las referidas a trampas en el buffer se enfocaron en los efectos de atrapamiento dinámico, y su impacto en el auto-calentamiento del dispositivo. Se presenta también un modelo que describe el atrapamiento y liberación de trampas en la barrera: mientras que el atrapamiento se debe a un túnel directo del electrón desde el metal de puerta, el desatrapamiento consiste en la emisión del electrón en la banda de conducción mediante túnel asistido por fonones. El modelo también simula la corriente de puerta, debida a la emisión electrónica dependiente de la temperatura y el campo eléctrico. Además, también se ilustra la corriente de drenador dependiente de la temperatura y el campo eléctrico. ABSTRACT GaN and AlN are group III-V piezoelectric semiconductor materials. The AlGaN/GaN heterojunction presents large piezoelectric and spontaneous polarization charge at the interface, leading to high 2DEG density close to the interface. A high power output would be obtained due to the high 2DEG density and mobility, which leads to elevated lattice temperature. The gate and drain biases induce converse piezoelectric stress that can influence the piezoelectric polarization charge and further influence the 2DEG density and output characteristics. Therefore, the device physics is relevant to all the electrical, thermal, and mechanical aspects. In this dissertation, by using the commercial finite-element-method (FEM) software COMSOL, we achieved the GaN HEMTs simulation with electro-thermal, electro-mechanical, and electro-thermo-mechanical full coupling. The coupling parts include the drift-diffusion model for the electron transport, the thermal conduction, and the piezoelectric effect. By simulations and some experimental characterizations, we have studied the device thermal, stress, and traps effects described in the following. The device geometry impact on the self-heating was studied by electro-thermal simulations and electrical characterizations. Among the obtained interesting results, we found that, for same power output, the distance between the gate and drain contact can influence distribution of the heat generation in the channel and thus influence the channel temperature. Diamond possesses high thermal conductivity. Integrated diamond with the device can spread the generated heat and thus potentially reduce the device self-heating effect. Electro-thermal simulations on this topic were performed. For the diamond integration on top of the device (top-side heat spreading), the determinant factors for the heat spreading ability are the diamond thickness, its thermal conductivity, and its distance to the heat source. The top-side heat spreading can also reduce the impact of thermal boundary resistance between the buffer and the substrate on the device thermal behavior. The very low electrical conductivity of diamond allows that it can directly contact the gate metal (which is very close to the heat source), being quite convenient to reduce the self-heating for the device under pulsed bias. Also, the diamond coated in vias etched in the substrate as heat spreading path (back-side heat spreading) was simulated. A competing mechanism influences the heat spreading ability, i.e., the etched vias would increase the device temperature due to the reduced heat sink while the coated diamond would decrease the device temperature due to its higher thermal conductivity. Therefore, relative thick coated diamond is needed in order to reduce the self-heating effect. The simulated local stress at the gate edge of the drain side for the device with standard and field plate gate structure were compared, which would be relevant to the device mechanical failure. Other stress simulations focused on the intrinsic stress in the diamond capping layer impact on the device electrical behaviors. The simulated stress and electrical output characteristics were compared to experimental data obtained by micro-Raman spectroscopy and electrical characterization, respectively. Results showed that the intrinsic stress in the capping layer caused the non-uniform distribution of 2DEG in the channel and the access region. Besides the enhancement of the device power output, intrinsic stress in the capping layer can potentially improve the device reliability by modulating the local stress at the gate edge of the drain side. Finally, the surface, buffer, and barrier traps effects were simulated in this work. Pulsed measurements showed that long gates and distances between gate and drain contact can increase the gate lag ratio (decrease the current collapse). This was explained by simulations on the surface traps effect. The simulations on buffer traps effects focused on illustrating the dynamic trapping/detrapping in the buffer and the self-heating impact on the device transient drain current. A model was presented to describe the trapping and detrapping in the barrier. The trapping was the electron direct tunneling from the gate metal while the detrapping was the electron emission into the conduction band described by phonon-assisted tunneling. The reverse gate current was simulated based on this model, whose mechanism can be attributed to the temperature and electric field dependent electron emission in the barrier. Furthermore, the mechanism of the device bias via the self-heating and electric field impact on the electron emission and the transient drain current were also illustrated.

A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Collimated Field Emission Beams from Metal Double-Gate Nanotip Arrays Optically Excited via Surface Plasmon Resonance

The generation of collimated electron beams from metal double-gate nanotip arrays excited by near infrared laser pulses is studied. Using electromagnetic and particle tracking simulations, we showed that electron pulses with small rms transverse velocities are efficiently produced from nanotip arrays by laser-induced field emission with the laser wavelength tuned to surface plasmon polariton resonance of the stacked double-gate structure. The result indicates the possibility of realizing a metal nanotip array cathode that outperforms state-of-the-art photocathodes.

Numerical study of the laser-tip coupling in surface plasmon assisted stacked-double-gate field emitter arrays

Recently, sub-wavelength-pitch stacked double-gate metal nanotip arrays have been proposed to realize high current, high brightness electron bunches for ultrabright cathodes for x-ray free-electron laser applications. With the proposed device structure, ultrafast field emission of photoexcited electrons is efficiently driven by vertical incident near infrared laser pulses, via near field coupling of the surface plasmon polariton resonance of the gate electrodes with the nanotip apex. In this work, in order to gain insight in the underlying physical processes, the authors report detailed numerical studies of the proposed device. The results indicate the importance of the interaction of the double-layer surface plasmon polariton, the position of the nanotip, as well as the incident angle of the near infrared laser pulses.

Field emission properties of carbon nanotube arrays with defects and impurities

Field emission from carbon nanotubes (CNTs) in the form of arrays or thin films give rise to several strongly correlated process of electromechanical interaction and degradation. Such processes are mainly due to (1) electron-phonon interaction (2) electromechanical force field leading to stretching of CNTs (3) ballistic transport induced thermal spikes, coupled with high dynamic stress, leading to degradation of emission performance at the device scale. Fairly detailed physics based models of CNTs considering the aspects (1) and (2) above have already been developed by these authors, and numerical results indicate good agreement with experimental results. What is missing in such a system level modeling approach is the incorporation of structural defects and vacancies or charge impurities. This is a practical and important problem due to the fact that degradation of field emission performance is indeed observed in experimental I-V curves. What is not clear from these experiments is whether such degradation in the I-V response is due to dynamic reorientation of the CNTs or due to the defects or due to both of these effects combined. Non-equilibrium Green’s function based simulations using a tight-binding Hamiltonian for single CNT segment show up the localization of carrier density at various locations of the CNTs. About 11% decrease in the drive current with steady difference in the drain current in the range of 0.2-0.4V of the gate voltage was reported in literature when negative charge impurity was introduced at various locations of the CNT over a length of ~20nm. In the context of field emission from CNT tips, a simplistic estimate of defects have been introduced by a correction factor in the Fowler-Nordheim formulae. However, a more detailed physics based treatment is required, while at the same time the device-scale simulation is necessary. The novelty of our present approach is the following. We employ a concept of effective stiffness degradation for segments of CNTs, which is due to structural defects, and subsequently, we incorporate the vacancy defects and charge impurity effects in the Green’s function based approach. Field emission induced current-voltage characteristics of a vertically aligned CNT array on a Cu-Cr substrate is then simulated using a detailed nonlinear mechanistic model of CNTs coupled with quantum hydrodynamics. An array of 10 vertically aligned and each 12 m long CNTs is considered for the device scale analysis. Defect regions are introduced randomly over the CNT length. The result shows the decrease in the longitudinal strain due to defects. Contrary to the expected influence of purely mechanical degradation, this result indicates that the charge impurity and hence weaker transport can lead to a different electromechanical force field, which ultimately can reduce the strain. However, there could be significant fluctuation in such strain field due to electron-phonon coupling. The effect of such fluctuations (with defects) is clearly evident in the field emission current history. The average current also decreases significantly due to such defects.

Efficient field emission from triode-type 1D arrays of carbon nanotubes.

Carbon nanotube (CNT) emitters were formed on line-patterned cathodes in microtrenches through a thermal CVD process. Single-walled carbon nanotubes (SWCNTs) self-organized along the trench lines with a submicron inter-CNT spacing. Excellent field emission (FE) properties were obtained: current densities at the anode (J(a)) of 1 microA cm(-2), 10 mA cm(-2) and 100 mA cm(-2) were recorded at gate voltages (V(g)) of 16, 25 and 36 V, respectively. The required voltage difference to gain a 1:10 000 contrast of the anode current was as low as 9 V, indicating that a very low operating voltage is possible for these devices. Not only a large number of emission sites but also the optimal combination of trench structure and emitter morphology are crucial to achieve the full FE potential of thin CNTs with a practical lifetime. The FE properties of 1D arrays of CNT emitters and their optimal design are discussed. Self-organization of thin CNTs is an attractive prospect to tailor preferable emitter designs in FE devices.

High-density large-scale field emitter arrays for x-ray free electron laser cathodes

High brightness electron sources are of great importance for the operation of the hard X-ray free electron lasers. Field emission cathodes based on the double-gate metallic field emitter arrays (FEAs) can potentially offer higher brightness than the currently used ones. We report on the successful application of electron beam lithography for fabrication of the large-scale single-gate as well as double-gate FEAs. We demonstrate operational high-density single-gate FEAs with sub-micron pitch and total number of tips up to 106 as well as large-scale double-gate FEAs with large collimation gate apertures. The details of design, fabrication procedure and successful measurements of the emission current from the single- and double-gate cathodes are presented.

High-density metallic nano-emitter arrays and their field emission characteristics

We report the fabrication and field emission properties of high-density nano-emitter arrays with on-chip electron extraction gate electrodes and up to 106 metallic nanotips that have an apex curvature radius of a few nanometers and a the tip density exceeding 108 cm−2. The gate electrode was fabricated on top of the nano-emitter arrays using a self-aligned polymer mask method. By applying a hot-press step for the polymer planarization, gate–nanotip alignment precision below 10 nm was achieved. Fabricated devices exhibited stable field electron emission with a current density of 0.1 A cm−2, indicating that these are promising for applications that require a miniature high-brightness electron source.

Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Field Emission Properties of Carbon Nanotube Arrays with Defects and Impurities

It has been found experimentally that the results related to the collective field emission performance of carbon nanotube (CNT) arrays show variability. The emission performance depends on the electronic structure of CNTs (especially their tips). Due to limitations in the synthesis process, production of highly pure and defect free CNTs is very difficult. The presence of defects and impurities affects the electronic structure of CNTs. Therefore, it is essential to analyze the effect of defects on the electronic structure, and hence, the field emission current. In this paper, we develop a modeling approach for evaluating the effect of defects and impurities on the overall field emission performance of a CNT array. We employ a concept of effective stiffness degradation for segments of CNTs, which is due to structural defects. Then, we incorporate the vacancy defects and charge impurity effects in our Green's function based approach. Simulation results indicate decrease in average current due to the presence of such defects and impurities.

Degradation and Failure of Field Emitting Carbon Nanotube Arrays

It has been observed experimentally that the collective field emission from an array of Carbon Nanotubes (CNTs) exhibits fluctuation and degradation, and produces thermal spikes, resulting in electro-mechanical fatigue and failure of CNTs. Based on a new coupled multiphysics model incorporating the electron-phonon transport and thermo-electrically activated breakdown, a novel method for estimating accurately the lifetime of CNT arrays has been developed in this paper. The main results are discussed for CNT arrays during the field emission process. It is shown that the time-to-failure of CNT arrays increases with the decrease in the angle of tip orientation. This observation has important ramifications for such areas as biomedical X-ray devices using patterned films of CNTs.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.