295 resultados para Cache


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Cache-coherent non uniform memory access (ccNUMA) architecture is a standard design pattern for contemporary multicore processors, and future generations of architectures are likely to be NUMA. NUMA architectures create new challenges for managed runtime systems. Memory-intensive applications use the system’s distributed memory banks to allocate data, and the automatic memory manager collects garbage left in these memory banks. The garbage collector may need to access remote memory banks, which entails access latency overhead and potential bandwidth saturation for the interconnection between memory banks. This dissertation makes five significant contributions to garbage collection on NUMA systems, with a case study implementation using the Hotspot Java Virtual Machine. It empirically studies data locality for a Stop-The-World garbage collector when tracing connected objects in NUMA heaps. First, it identifies a locality richness which exists naturally in connected objects that contain a root object and its reachable set— ‘rooted sub-graphs’. Second, this dissertation leverages the locality characteristic of rooted sub-graphs to develop a new NUMA-aware garbage collection mechanism. A garbage collector thread processes a local root and its reachable set, which is likely to have a large number of objects in the same NUMA node. Third, a garbage collector thread steals references from sibling threads that run on the same NUMA node to improve data locality. This research evaluates the new NUMA-aware garbage collector using seven benchmarks of an established real-world DaCapo benchmark suite. In addition, evaluation involves a widely used SPECjbb benchmark and Neo4J graph database Java benchmark, as well as an artificial benchmark. The results of the NUMA-aware garbage collector on a multi-hop NUMA architecture show an average of 15% performance improvement. Furthermore, this performance gain is shown to be as a result of an improved NUMA memory access in a ccNUMA system. Fourth, the existing Hotspot JVM adaptive policy for configuring the number of garbage collection threads is shown to be suboptimal for current NUMA machines. The policy uses outdated assumptions and it generates a constant thread count. In fact, the Hotspot JVM still uses this policy in the production version. This research shows that the optimal number of garbage collection threads is application-specific and configuring the optimal number of garbage collection threads yields better collection throughput than the default policy. Fifth, this dissertation designs and implements a runtime technique, which involves heuristics from dynamic collection behavior to calculate an optimal number of garbage collector threads for each collection cycle. The results show an average of 21% improvements to the garbage collection performance for DaCapo benchmarks.

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Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.

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De nos jours, les séries télévisées américaines représentent une part incontournable de la culture populaire, à tel point que plusieurs traductions audiovisuelles coexistent au sein de la francophonie. Outre le doublage qui permet leur diffusion à la télévision, elles peuvent être sous titrées jusqu’à trois fois soit, en ordre chronologique : par des fans sur Internet; au Québec, pour la vente sur DVD en Amérique du Nord; et en France, pour la vente sur DVD en Europe. Pourtant, bien que ces trois sous titrages répondent aux mêmes contraintes linguistiques (celles de la langue française) et techniques (diffusion au petit écran), ils diffèrent dans leur traitement des dialogues originaux. Nous établissons dans un premier temps les pratiques à l’œuvre auprès des professionnels et des amateurs. Par la suite, l’analyse des traductions ainsi que le recours à un corpus comparable de séries télévisées françaises et québécoises permettent d’établir les normes linguistiques (notamment eu égard à la variété) et culturelles appliquées par les différents traducteurs et, subsidiairement, de définir ce que cache l’appellation « Canadian French ». Cette thèse s’inscrit dans le cadre des études descriptives et sociologiques. Nous y décrivons la réalité professionnelle des traducteurs de l’audiovisuel et l’influence que les fansubbers exercent non seulement sur la pratique professionnelle, mais aussi sur de nouvelles méthodes de formation de la prochaine génération de traducteurs. Par ailleurs, en étudiant plusieurs traductions d’une même œuvre, nous démontrons que les variétés de français ne sauraient justifier, à elles seules, la multiplication de l’offre en sous titrage, vu le faible taux de différences purement linguistiques.

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Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation due to high contention scenarios and different hardware and operating system limitations that abort transactions, e.g. cache overflows, hardware and software exceptions, etc. To deal with these events and to ensure forward progress, BE-HTM systems usually provide a software fallback path to execute a lock-based version of the code. In this paper, we propose a hardware implementation of an irrevocability mechanism as an alternative to the software fallback path to gain insight into the hardware improvements that could enhance the execution of such a fallback. Our mechanism anticipates the abort that causes the transaction serialization, and stalls other transactions in the system so that transactional work loss is mini- mized. In addition, we evaluate the main software fallback path approaches and propose the use of ticket locks that hold precise information of the number of transactions waiting to enter the fallback. Thus, the separation of transactional and fallback execution can be achieved in a precise manner. The evaluation is carried out using the Simics/GEMS simulator and the complete range of STAMP transactional suite benchmarks. We obtain significant performance benefits of around twice the speedup and an abort reduction of 50% over the software fallback path for a number of benchmarks.

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Ce mémoire de recherche-création est accompagné du court métrage «Tala». Pour visionner en ligne : vimeo.com/ondemand/talapierphilippechevigny

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Ce mémoire de recherche-création est accompagné du court métrage «Tala». Pour visionner en ligne : vimeo.com/ondemand/talapierphilippechevigny

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Background: The most frequent viral diseases which can cause abortion in sheep are Blue tongue, Border disease virus, Cache Valley fever and Schmallenberg virus. The diagnosis of abortion, namely virus-induced represents a challenge to field clinicians, since clinical signs presented by the dam are discrete, non-specific and variable (Agerhom et al., 2015). On the other hand, while some foetuses reveal characteristic and visible malformations, others do not reveal any lesions. In face of it, definitive diagnosis requires an appropriate history collection, as well as sending fresh samples, namely abortion material, foetus, placenta and umbilical cord, to a specialty laboratory, to obtain a precise diagnosis. Objectives: The authors suggest a registration method of all mandatory data, in order to further assist the diagnosis of viral diseases at the laboratories, including the most frequent congenital malformations reported in sheep abortions. Methods: Abortion samples of suspected viral origin were collected and all data were registered, in worktables optimized for this purpose. Results: The authors document, using macroscopic figures lesions of malformations in abortions, emphasizing the frequency and the importance of documenting each case, proposing practical and effective worktables to assist the fieldwork. Conclusions: Field clinician’s awareness of the importance of early detection of viral diseases causing abortion outbreaks stimulates a proper data collection for each case of abortion, in order to contribute to a precise diagnosis and posterior consistent epidemiological studies, which may allow diminishing of economic losses.

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Die Dissertation befasst sich mit der Verantwortlichkeit und der Haftungsprivilegierung von Internet Service Providern (ISP) für Urheberrechtsverletzungen Dritter im deutschen und US-amerikanischen Recht. Internet Service Provider (das sind Host-Provider, Cache-Provider, Access-Provider sowie Suchmaschinen-Anbieter bzw. sonstige Linksetzende) nehmen eine wichtige Rolle im Internet ein. In Deutschland sehen sich die ISP jedoch trotz gesetzlicher Haftungsprivilegien erheblichen Rechtsunsicherheiten ausgesetzt. Der Dissertation liegt die Hypothese zugrunde, dass durch die Ausweitung der Verantwortlichkeit der ISP durch die Rechtsprechung die gesetzlich stipulierte Haftungsprivilegierung faktisch entwertet wird. Insbesondere stehen die Nichtanwendung der Privilegien auf Unterlassungsansprüche sowie die im Rahmen der Störerhaftung begründeten Prüfpflichten der Intention des Gesetzgebers (auch auf europäischer Ebene) entgegen. Eine gerechte Balance der Interessen der Akteure durch die Rechtsprechung wurde nicht erreicht. Die gesetzliche Ausgestaltung der US-amerikanischen Privilegierung verspricht hingegen eine den Interessen der ISP gerechtere Lösung. Auch die Rechtsanwendung der US-amerikanischen Gerichte liegt hiermit auf einer Linie.

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En este estudio se pretende exponer la situación actual de los derechos de propiedad de los bienes inmuebles rurales, principalmente bienes baldíos. Se parte de la base de los regímenes que han existido, sus principales características, su estado actual, la productividad económica de los mismos en determinadas regiones de Colombia, su seguridad jurídica y se planteará una propuesta de mejoramiento que podría obtener mejores resultados, tanto sociales como económicos, soportado en la experiencia del autor y en los diversos estudios que se han efectuado sobre el tema a nivel mundial.

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La enfermedad de Alzheimer (EA) es la demencia más frecuente y su prevalencia continúa en aumento tanto en Colombia como en el mundo. Esta investigación tuvo como objetivo explorar si las actitudes hacia la EA varían según la edad y género de 450 personas adultas colombianas. Se realizó un estudio exploratorio de corte transversal en el que se aplicó un cuestionario autodiligenciado. Se encontró que efectivamente hay algunas diferencias según la edad y el género en el componente cognoscitivo (creencias y conocimiento) y conductual (intención conductual y conducta) de las actitudes; y diferencias según el género en el componente afectivo. Se concluye que los conocimientos sobre la EA son escasos, que la tristeza es la emoción predominante hacia la EA y que es un tema de interés en el que predomina la idea de que afecta especialmente la memoria. Se discutieron los resultados reconociendo que esta es una aproximación inicial a las actitudes hacia la EA.