Modifiable barriers to leisure-time physical activity during pregnancy: a qualitative study investigating first time mother's views and experiences

BACKGROUND: Evidence suggests physical activity often declines during pregnancy, however explanations for the decline are not well understood. The aim of this study was to identify modifiable barriers to leisure-time physical activity among women who did not meet physical activity guidelines during pregnancy. METHODS: Analyses were based on data from 133 mothers (~3-months postpartum) who were recruited from the Melbourne InFANT Extend study (2012/2013). Women completed a self-report survey at baseline in which they reported their leisure-time physical activity levels during pregnancy as well provided an open-ended written response regarding the key barriers that they perceived prevented them from meeting the physical activity guidelines during their pregnancy. Thematic analyses were conducted to identify key themes. RESULTS: The qualitative data revealed six themes relating to the barriers of leisure-time physical activity during pregnancy. These included work-related factors (most commonly reported), tiredness, pregnancy-related symptoms, being active but not meeting the guidelines, lack of motivation, and a lack of knowledge of recommendations. CONCLUSION: Considering work-related barriers were suggested to be key factors to preventing women from meeting the physical activity guidelines during pregnancy, workplace interventions aimed at providing time management skills along with supporting physical activity programs for pregnant workers should be considered. Such interventions should also incorporate knowledge and education components, providing advice for undertaking leisure-time physical activity during pregnancy.

Optimized Water Demand Management Through Intelligent Sensing And Analytics: The WISDOM Approach

New business and technology platforms are required to sustainably manage urban water resources [1,2]. However, any proposed solutions must be cognisant of security, privacy and other factors that may inhibit adoption and hence impact. The FP7 WISDOM project (funded by the European Commission - GA 619795) aims to achieve a step change in water and energy savings via the integration of innovative Information and Communication Technologies (ICT) frameworks to optimize water distribution networks and to enable change in consumer behavior through innovative demand management and adaptive pricing schemes [1,2,3]. The WISDOM concept centres on the integration of water distribution, sensor monitoring and communication systems coupled with semantic modelling (using ontologies, potentially connected to BIM, to serve as intelligent linkages throughout the entire framework) and control capabilities to provide for near real-time management of urban water resources. Fundamental to this framework are the needs and operational requirements of users and stakeholders at domestic, corporate and city levels and this requires the interoperability of a number of demand and operational models, fed with data from diverse sources such as sensor networks and crowsourced information. This has implications regarding the provenance and trustworthiness of such data and how it can be used in not only the understanding of system and user behaviours, but more importantly in the real-time control of such systems. Adaptive and intelligent analytics will be used to produce decision support systems that will drive the ability to increase the variability of both supply and consumption [3]. This in turn paves the way for adaptive pricing incentives and a greater understanding of the water-energy nexus. This integration is complex and uncertain yet being typical of a cyber-physical system, and its relevance transcends the water resource management domain. The WISDOM framework will be modeled and simulated with initial testing at an experimental facility in France (AQUASIM – a full-scale test-bed facility to study sustainable water management), then deployed and evaluated in in two pilots in Cardiff (UK) and La Spezia (Italy). These demonstrators will evaluate the integrated concept providing insight for wider adoption.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Project management in cloud

Este proyecto consiste en la construcción de un prototipo para la gestión de proyectos, destinada a usuarios del entorno profesional. La herramienta pretende servir de soporte a los equipos que realicen un proyecto dotando al usuario con la posibilidad de gestionar los tiempos del proyecto, gestión de requisitos, gestión de recursos, gestión de la documentación, etc. Adicionalmente, este trabajo llevará asociado un plan de negocio para poder estudiar la viabilidad del proyecto, en este plan de negocio se analizará; el entorno externo (competencia); análisis de las debilidades, fortalezas, amenazas y oportunidades; plan de marketing; plan económicofinanciero; análisis de riesgos del proyecto. A grandes rasgos, la herramienta desarrollada se compone de dos bases de datos (una relacional y otra no relacional), un conjunto de módulos que implementan la funcionalidad y una interfaz gráfica que proporciona a los usuarios una forma cómoda de interactuar con el sistema, principalmente ofrecerá las siguientes opciones:  Gestión de proyectos  Gestión de usuarios.  Gestión de recursos  Gestión de tiempos  Cuadro de mando y notificaciones. ---ABSTRACT---This Project consist of the construction of a prototype for Project management, intended for users of the profesional environment. The software aims to support teams conducting a project by providing the user with the ability to manage time, requirements management, resource management, document management, etc. In addition, this work includes a business plan to study the viability of the project. This business plan addresses the following; analysis of the external enviroment; analysis of the strengths, weaknesses, opportunities and threats; marketing plan; economic and financial plan; analysis of project risks. In general terms, the developed tools are composed of two databases (relational and nonrelational), a set of modules that implement the functionality and a web interface that gives users a convenient way to interact with the system. The options that the system offers are:  Project management  User management  Resource management  Time management  Dashboard and notifications

How to write successful business and management essays

How to Write Successful Business and Management Essays is a systematic guide to successfully producing written work for business and management degrees. The authors address the all too common pitfalls of essay assignments, as well as providing students with a step-by-step programme to approach essay questions, both in coursework and exam contexts. Starting with the basics this book helps develop skills through the use of examples, exercises and checklists. Helpful features include: - Annotated essay examples, showing both good and bad points - Tips on time management and motivation, note taking and effective reading - Final checklists to use before you hand in - Explanation of what the markers are looking for – and how to give it to them Many students find referencing particularly confusing so the book provides detailed but easy-to-use information on what referencing is and how to do it properly.

Validation Française de l’Échelle de la Personnalité Temporelle (French Validation of the Time Personality Indicator)

RÉSUMÉ Certains auteurs ont développé un intérêt pour la compréhension des aptitudes associées à la gestion du temps. Ainsi, plusieurs définitions théoriques ont été proposées afin de mieux cerner ce concept et une multitude de questionnaires a été développée afin de le mesurer. La présente étude visait à valider la traduction française d’un de ces outils, soit le Time Personality Indicator (TPI). Des analyses exploratoires et confirmatoires ont été effectuées sur l’ensemble des données recueillies auprès de 1 267 étudiants et employés de l’Université Laval ayant complété la version française du TPI ainsi que d’autres mesures de la personnalité. Les résultats ont révélé qu’une solution à huit facteurs permet de mieux décrire les données de l’échantillon. La discussion présente les raisons pour lesquelles la version française du TPI est valide, identifie certaines limites de la présente étude et souligne l’utilité de cet outil pour la recherche sur la gestion du temps. (ABSTRACT: Numerous authors have developed an interest towards the understanding of the abilities related to time management. As a consequence, multiple theoretical definitions have been proposed to explain time management. Likewise, several questionnaires have been developed in order to measure this concept. The aim of this study was to validate a French version of one of these tools, namely the Time Personality Indicator (TPI). The French version of the TPI and other personality questionnaires were completed by 1267 students and employees of Université Laval. The statistical approach used included exploratory and confirmatory analyses. Results revealed that an eight factor model provided a better adjustment to the data. The discussion provides arguments supporting the validity of the French version of the TPI and underlines the importance of such a tool for the research on time management)

They also serve who only stand and wait

Purpose Waiting for service by customers is an important problem for many financial service marketers. Two new approaches are proposed. First, customer evaluation of the service is increased with an ambient scent. Second a cognitive variable is identified which different iates customers by the way they value time so that they can be segmented. Methodology Pretests included focus groups which highlighted financial services and a pilot test were foll owed by a main sample of 607 subjects. Structural equation modelling and multivariate analysis of covariance were used for analysis. Findings A cognitive variable, the need for time management can be used, together with demographic and customer net worth data, to segment a customer base. Two environmental interventions, music and scent, can increase customer satisfaction among customers kept waiting in a line. Research implications Two original approaches to a rapidly growing service marketing problem are identified. Practical implications Service contact points can reduce incidence of "queue rage" and enhance customer satisfaction by either or both of two simple modifications to the service environment or a preventive strategy of offering targeted customers an alternative. Originality A new method of segmentation and a new environmental intervention are proposed .

A life jacket with holes- : a case study of 'temporary engagement' : a strategy used by Education Queensland to employ beginning secondary teachers

This research investigated the impact of Education Queensland's employment policy and practices for beginning secondary teachers appointed on temporary engagement. The context was the public secondary school sector within the state of Queensland, Australia. The study was set within a context of the changing nature of work from full-time permanent employment towards casual, fixed-term contracts, temporary and part-time employment, a trend reflected in the employment patterns for teachers within Australia. Two broad categories of literature relating to the research problem of this thesis were reviewed, namely the beginning teacher and permanency or tenure. The focus in the research literature on beginning teachers was the professional experiences of teachers within the classroom and school. There was a paucity of research that considered the working and industrial conditions of temporary employment for beginning teachers or the personal and professional implications of this form of employment. The review of the context and literature was conceptualised as a Beginning Temporary Teacher Theoretical Framework which served to inform the study. Using a qualitative case study methodology, the research techniques employed for the thesis were semi-structured interview and document analysis. A simultaneously conducted research project in which the researcher participated entitled 'Winning the Lottery? Beginning Teachers on Temporary Engagement' foregrounded this thesis in terms of refining the research question, contributing to the literature and in the selection of the participants. For this case study the perspectives of four distinct yet inter-related categories of professionals were sought. These included four beginning secondary teachers, three school administrators, a Senior Personnel Officer with Education Queensland, and a representative from the Queensland Teachers' Union. The research findings indicated that none of the beginning teachers or other professionals viewed starting a career in teaching on temporary engagement as the ideal. The negative features identified were the differential treatment received and the high level of uncertainty associated with temporary employment. Differential treatment tended to indicate 'less' entitlements, in terms of access to induction and professional development, recreational and sick leave, acceptance by and expectations of other colleagues, and avenues of redress in grievance cases. Moreover, interviews indicated a high level of uncertainty in terms of starting within the teaching profession, commencing at a new school, and a regular income. In addition, frequent changes in schools and/or cohorts of students exacerbated levels of uncertainty. The beginning teachers reported significantly decreased motivation, self-esteem and sense of belonging, and increased stress levels. There was an even more marked negative impact on those beginning teachers who had experienced a higher number of temporary engagements and schools in their first year of teaching. Conversely, strong staff support and a reasonable length of time in the one school improved the quality of the beginning teachers' experiences. The overall impact of being on temporary engagement resulted in delayed permanent position appointments, decreased commitment to particular schools and to Education Queensland as the employing authority, and for two of the beginning teachers, it produced a desire to seek alternative employment. The implementation of Education Queensland's policies relating to working conditions and entitlements for these temporary beginning teachers at the school level was revealed to be less than satisfactory. There was a tendency towards 'just-in- time' management of the beginning teacher on temporary engagement. The beginning teachers received 'less-than-messages' about access to and use of departmental documentation, support through induction and professional development, and their transition from temporary to permanent employment. To ensure a more systematic, supportive and inclusive process for managing the temporary beginning teacher, a conceptual framework entitled 'Continuums of Tension' was developed. The four continuums included permanent employment - temporary employment; system perspective - individual perspective; teaching as a profession - teaching as a job; and the permanent beginning teacher - university graduate. The general principles of the human resource policies of Education Queensland were based on a commitment to permanent employment, a system's perspective, viewing teaching as a profession and a homogeneous group of permanent beginning teachers. Contrasting with this, the beginning teacher on temporary engagement tended to operate from the position of temporary employment and a perspective that was individually based. Their priorities therefore included the 'occupational' aspects of being a temporary teacher striving to become permanent. Thus there existed a tension or contradiction between the general principles of human resource policies within Education Queensland and the employment experiences of beginning teachers on temporary engagement. The study proposed three actions for resolution to address the aforementioned tensions. The actions included: (a) the effective provision and targeted communication of information; (b) support, induction and professional development; and (c) a coordinated approach between Education Queensland, Queensland Teachers' Union, the Universities and the beginning teacher. These actions are fm1her refined to include: (a) an induction kit to suppm1 the individual through the pre-employment to permanent employee phases, (b) an extrapolation of the roles and responsibilities of Education Queensland personnel charged with supporting the beginning temporary teacher, and (c) a series of recommendations to effect a coordinated approach amongst the key stakeholders. The theoretical and conceptual frameworks have provided a means of addressing the identified needs of the beginning teacher on temporary engagement. As such, this study has contributed to the research literature on teacher employment and professionalism and aims to provide a beginning temporary teacher with managed professional and occupational support.

Uncovering the evidence of non-expert nephrology nursing practice

Expertise in nursing has been widely studied although there have been no previous studies into what constitutes expertise in nephrology (renal) nursing. This paper, which is abstracted from a larger study into the acquisition and exercise of nephrology nursing expertise, provides evidence of the characteristics and practices of non-expert nephrology nurses. Using the grounded theory method, the study took place in one renal unit in New South Wales, Australia, and involved six non-expert and 11 expert nurses. Sampling was purposive then theoretical. Simultaneous data collection and analysis using participant observation, review of nursing documentation and semistructured interviews was undertaken. The study revealed a three-stage skills-acquisitive process that was identified as non-expert, experienced non-expert and expert stages. Non-expert nurses showed superficial nephrology nursing knowledge and limited experience; they were acquiring basic nephrology nursing skills and possessed a narrow focus of practice.

Getting in the Groove : The Recording Studio Procedural Guide

This paper examines time management in the recording studio from the perspective of the music producer. The paper is presented in the form of a guide that will provide a common language to music clientele and technical personnel to help achieve the best possible creative outcome. The research for the guide combined the author's experience, literary evidence and external assessment to work towards establishing a practical industry resource. The result of the study explored how the success of any recording project can be forecast before valuable resources are committed. The feedback from the survey group was positive and some professionals recognised an immediate application for the procedural guide, which exceeded the author's expectations.

Digital dietetics : practices and attitudes to technology use among Australian dietitians

Recent advancements in the capabilities of information and communication technologies (ICT) offer unique avenues to support the delivery of nutrition care. Despite ICTs being widely available, evidence on the practices and attitudes with regard to ICT use among dietitians is limited. A cross-sectional survey of Dietitians Association of Australia members was administered online in August 2011. All dietitians who responded (n=87) had access to a computer at work. Half reported providing non face-to-face consultations, with the telephone and email the most common modes of delivery. The use of smart phones was prevalent for 49% of practitioners, with 30% recommending nutrition-related applications and/or programs to clients. Benefits to technology use in practice most commonly reported included improvements in access to information/resources, time management, and workflow efficiency. Barriers identified related to cost and access to technology, and lack of suitable programs/applications. Technology was viewed as an important tool in practice among 93% of dietitians surveyed, however only 38% were satisfied with their current level of use. The majority (81%) believed more technology should be integrated within dietetics, while 85% indicated that the development of suitable and practical applications andprograms is necessary for future practice. Technology is regarded as an important tool by Australian dietitians, with an expressed need for theirinclusion to further facilitate nutrition care. Regular and ongoing evaluation of technology use among dietitians is vital to ensure thatapplications and use are evidence based and relevant to consumers in the digital world.

Intern underperformance is detected more frequently in emergency medicine rotations

Objective: To determine the frequency and nature of intern underperformance as documented on in-training assessment forms. Methods: A retrospective review of intern assessment forms from a 2 year period (2009–2010) was conducted at a tertiary referral hospital in Brisbane, Queensland. The frequency of interns assessed as ‘requiring substantial assistance’ and/or ‘requires further development’ on mid- or end-of-term assessment forms was determined. Forms were analysed by the clinical rotation, time of year and domain(s) of clinical practice in which underperformance was documented. Results: During 2009 and 2010 the overall documented incidence of intern underperformance was 2.4% (95% CI 1.5–3.9%). Clinical rotation in emergency medicine detected significantly more underperformance compared with other rotations (P < 0.01). Interns predominantly had difficulty with ‘clinical judgment and decision-making skills’, ‘time management skills’ and ‘teamwork and colleagues’ (62.5%, 55% and 32.5% of underperforming assessments, respectively). Time of the year did not affect frequency of underperformance. A proportion of 13.4% (95% CI 9.2–19.0%) of interns working at the institution over the study period received at least one assessment in which underperformance was documented. Seventy-six per cent of those interns who had underperformance identified by mid-term assessment successfully completed the term following remediation. Conclusion: The prevalence of underperformance among interns is low, although higher than previously suggested. Emergency medicine detects relatively more interns in difficulty than other rotations.

Validation and consistency in the application of a trauma team activation system at a level 1 trauma centre

- The RAH was activated over 2500 trauma calls in 2009. This figure is over twice the number of calls put out by similar services. - Many trauma calls (in particular L2 trauma calls) from the existing system do not warrant activation of the trauma team - Sometimes trauma calls are activated for nontrauma reasons (eg rapid access to radiology, departmental pressures etc) - The excess of trauma calls has several deleterious effects particularly on time management for the trauma service staff: ward rounds/tertiary survey rounds, education, quality improvement, research

Soliciting additional concerns in the primary care consultation and the utility of a brief communication intervention to aid solicitation: A qualitative study

Objective To investigate the perspectives of general practitioners (GPs) on the practice of soliciting additional concerns (ACs) and the acceptability and utility of two brief interventions (prompts) designed to aid the solicitation. Methods Eighteen GPs participating in a feasibility randomised controlled trial were interviewed. Interviews were semi-structured and audio-recorded. Data were analysed using a Framework Approach. Results Participants perceived eliciting ACs as important for: reducing the need for multiple visits, identifying serious illness early, and increasing patient and GP satisfaction. GPs found the prompts easy to use and some continued their use after the study had ended to aid time management. Others noted similarities between the intervention and their usual practice. Nevertheless, soliciting ACs in every consultation was not unanimously supported. Conclusion The prompts were acceptable to GPs within a trial context, but there was disagreement as to whether ACs should be solicited routinely. Some GPs considered the intervention to aid their prioritisation efficiency within consultations. Practice implications Some GPs will find prompts which encourage ACs to be solicited early in the consultation enable them to better organise priorities and manage time-limited consultations more effectively.

'... the walls fell down but the blokes just coded ...' - Varieties of stability in software product development during organizational restructurings

Many Finnish IT companies have gone through numerous organizational changes over the past decades. This book draws attention to how stability may be central to software product development experts and IT workers more generally, who continuously have to cope with such change in their workplaces. It does so by analyzing and theorizing change and stability as intertwined and co-existent, thus throwing light on how it is possible that, for example, even if ‘the walls fall down the blokes just code’ and maintain a sense of stability in their daily work. Rather than reproducing the picture of software product development as exciting cutting edge activities and organizational change as dramatic episodes, the study takes the reader beyond the myths surrounding these phenomena to the mundane practices, routines and organizings in product development during organizational change. An analysis of these ordinary practices offers insights into how software product development experts actively engage in constructing stability during organizational change through a variety of practices, including solidarity, homosociality, close relations to products, instrumental or functional views on products, preoccupations with certain tasks and humble obedience. Consequently, the study shows that it may be more appropriate to talk about varieties of stability, characterized by a multitude of practices of stabilizing rather than states of stagnation. Looking at different practices of stability in depth shows the creation of software as an arena for micro-politics, power relations and increasing pressures for order and formalization. The thesis gives particular attention to power relations and processes of positioning following organizational change: how social actors come to understand themselves in the context of ongoing organizational change, how they comply with and/or contest dominant meanings, how they identify and dis-identify with formalization, and how power relations often are reproduced despite dis-identification. Related to processes of positioning, the reader is also given a glimpse into what being at work in a male-dominated and relatively homogeneous work environment looks like. It shows how the strong presence of men or “blokes” of a particular age and education seems to become invisible in workplace talk that appears ‘non-conscious’ of gender.