Highly efficient silicon nanoarray solar cells by a single-step plasma-based process

Highly efficient solar cells (conversion efficiency 11.9%, fill factor 70%) based on the vertically aligned single-crystalline nanostructures are fabricated without any pre-fabricated p-n junctions in a very simple, single-step process of Si nanoarray formation by etching p-type Si(100) wafers in low-temperature environment-friendly plasmas of argon and hydrogen mixtures.

Silicon on silicon : self-organized nanotip arrays formed in reactive Ar+H2 plasmas

The formation of arrays of vertically aligned nanotips on a moderately heated (up to 500 degrees C) Si surface exposed to reactive low-temperature radio frequency (RF) Ar+H(2) plasmas is studied. It is demonstrated that the nanotip surface density, aspect ratio and height dispersion strongly depend on the substrate temperature, discharge power, and gas composition. It is shown that nanotips with aspect ratios from 2.0 to 4.0 can only be produced at a higher RF power density (41.7 mW cm(-3)) and a hydrogen content of about 60%, and that larger aspect ratios can be achieved at substrate temperatures of about 300 degrees C. The use of higher (up to 500 degrees C) temperatures leads to a decrease of the aspect ratio but promotes the formation of more uniform arrays with the height dispersion decreasing to 1.5. At lower (approximately 20 mW cm(-3)) RF power density, only semispherical nanodots can be produced. Based on these experimental results, a nanotip formation scenario is proposed suggesting that sputtering, etching, hydrogen termination, and atom/radical re-deposition are the main concurrent mechanisms for the nanostructure formation. Numerical calculations of the ion flux distribution and hydrogen termination profiles can be used to predict the nanotip shapes and are in a good agreement with the experimental results. This approach can be applied to describe the kinetics of low-temperature formation of other nanoscale materials by plasma treatment.

Dual yolk-shell structure of carbon and silica-coated silicon for high-performance lithium-ion batteries

Silicon batteries have attracted much attention in recent years due to their high theoretical capacity, although a rapid capacity fade is normally observed, attributed mainly to volume expansion during lithiation. Here, we report for the first time successful synthesis of Si/void/SiO2/void/C nanostructures. The synthesis strategy only involves selective etching of SiO2 in Si/SiO2/C structures with hydrofluoric acid solution. Compared with reported results, such novel structures include a hard SiO2-coated layer, a conductive carbon-coated layer, and two internal void spaces. In the structures, the carbon can enhance conductivity, the SiO2 layer has mechanically strong qualities, and the two internal void spaces can confine and accommodate volume expansion of silicon during lithiation. Therefore, these specially designed dual yolk-shell structures exhibit a stable and high capacity of 956 mA h g−1 after 430 cycles with capacity retention of 83%, while the capacity of Si/C core-shell structures rapidly decreases in the first ten cycles under the same experimental conditions. The novel dual yolk-shell structures developed for Si can also be extended to other battery materials that undergo large volume changes.

A silicon micromachined photonic band gap cell, characteristics and an application

A novel PBG cell based on micromachining of Silicon using wet anisotropic etching has been considered. Since this is based on etching of the Silicon substrate, it is amenable to fabrication with standard Silicon processes and integration with millimeter wave circuits. We characterize this kind of PBG cell by full wave simulations using a time domain code. For the purpose of characterization, the scenario of a 50 ohm microstrip line placed on a Silicon substrate which is anisotropically etched to create patterns with sloping walls is considered. This is shown to produce the well known PBG response of stop bands in certain frequency bands. We look at the variation in the transmission coefficient (S-21) response as the number of periods, length based average fill factor and depth of micromachining are varied. One application of a low pass filter has been proposed and simulated results are given.

Realization of thermally durable close-packed 2D gold nanoparticle arrays using self-assembly and plasma etching

Realization of thermally and chemically durable, ordered gold nanostructures using bottom-up self-assembly techniques are essential for applications in a wide range of areas including catalysis, energy generation, and sensing. Herein, we describe a modular process for realizing uniform arrays of gold nanoparticles, with interparticle spacings of 2 nm and above, by using RF plasma etching to remove ligands from self-assembled arrays of ligand-coated gold nanoparticles. Both nanoscale imaging and macroscale spectroscopic characterization techniques were used to determine the optimal conditions for plasma etching, namely RF power, operating pressure, duration of treatment, and type of gas. We then studied the effect of nanoparticle size, interparticle spacing, and type of substrate on the thermal durability of plasma-treated and untreated nanoparticle arrays. Plasma-treated arrays showed enhanced chemical and thermal durability, on account of the removal of ligands. To illustrate the application potential of the developed process, robust SERS (surface-enhanced Raman scattering) substrates were formed using plasma-treated arrays of silver-coated gold nanoparticles that had a silicon wafer or photopaper as the underlying support. The measured value of the average SERS enhancement factor (2 x 10(5)) was quantitatively reproducible on both silicon and paper substrates. The silicon substrates gave quantitatively reproducible results even after thermal annealing. The paper-based SERS substrate was also used to swab and detect probe molecules deposited on a solid surface.

Fabrication of Highly Dense Nanoholes by Self-Assembled Gallium Droplet on Silicon Surface

We report the fabrication of nanoholes on silicon surface by exploiting the solubility of silicon in gallium by local droplet etching. Nanometer-sized gallium droplets yield nanoholes when annealed in ultra-high vacuum at moderate temperatures (similar to 500 degrees C) without affecting the other regions. High vacuum and moderate annealing temperatures are key parameters to obtain well-defined nanoholes with diameter comparable to that of Ga droplets. Self-assembly of Ga droplet leads to a nanohole density of 4-8 x 10(10)/cm(2).

Transfer free suspended graphene devices on silicon using electrodeposited copper

Transfer free processes using Cu films greatly simplify the fabrication of reliable suspended graphene devices. In this paper, the authors report on the use of electrodeposited Cu films on Si for transfer free fabrication of suspended graphene devices. The quality of graphene layers on optimized electrodeposited Cu and Cu foil are found to be the same. By selectively etching the underlying Cu, the authors have realized by a transfer free process metal contacted, suspended graphene beams up to 50 mu m in length directly on Si. The suspended graphene beams do not show any increase in defect levels over the as grown state indicating the efficiency of the transfer free process. Measured room temperature electronic mobilities of up to 5200 cm(2)/V.s show that this simpler and CMOS compatible route has the potential to replace the foil based route for such suspended nano and micro electromechanical device arrays. (C) 2014 American Vacuum Society.

Fabrication and characterization of gold coated hollow silicon microneedle array for drug delivery

In this paper, we present the fabrication and characterization of Ti and Au coated hollow silicon microneedles for transdermal drug delivery applications. The hollow silicon microneedles are fabricated using isotropic etching followed by anisotropic etching to obtain a tapered tip. Silicon microneedle of 300 mu m in height, with 130 mu m outer diameter and 110 mu m inner diameter at the tip followed by 80 mu m inner diameter and 160 mu m outer diameter at the base have been fabricated. In order to improve the biocompatibility of microneedles, the fabricated microneedles were coated with Ti (500 nm) by sputtering technique followed by gold coating using electroplating. A breaking force of 225 N was obtained for the fabricated microneedles, which is 10 times higher than the skin resistive force. Hence, fabricated microneedles can easily be inserted inside the skin without breakage. The fluid flow through the microneedles was studied for different inlet pressures. A minimum inlet pressure of 0.66 kPa was required to achieve a flow rate of 50 mu l in 2 s with de-ionized water as a fluid medium. (C) 2014 Elsevier B.V. All rights reserved.

Inductively coupled reactive ion etching studies on sputtered yttria stabilized zirconia thin films in SF6, Cl-2, and BCl3 chemistries

Downscaling of yttria stabilized zirconia (YSZ) based electrochemical devices and gate oxide layers requires successful pattern transfer on YSZ thin films. Among a number of techniques available to transfer patterns to a material, reactive ion etching has the capability to offer high resolution, easily controllable, tunable anisotropic/isotropic pattern transfer for batch processing. This work reports inductively coupled reactive ion etching studies on sputtered YSZ thin films in fluorine and chlorine based plasmas and their etch chemistry analyses using x-ray photoelectron spectroscopy. Etching in SF6 plasma gives an etch rate of 7 nm/min chiefly through physical etching process. For same process parameters, in Cl-2 and BCl3 plasmas, YSZ etch rate is 17 nm/min and 45 nm/min, respectively. Increased etch rate in BCl3 plasma is attributed to its oxygen scavenging property synergetic with other chemical and physical etch pathways. BCl3 etched YSZ films show residue-free and smooth surface. The surface atomic concentration ratio of Zr/Y in BCl3 etched films is closer to as-annealed YSZ thin films. On the other hand, Cl-2 etched films show surface yttrium enrichment. Selectivity ratio of YSZ over silicon (Si), silicon dioxide (SiO2) and silicon nitride (Si3N4) are 1:2.7, 1:1, and 1:0.75, respectively, in BCl3 plasma. YSZ etch rate increases to 53 nm/min when nonoxygen supplying carrier wafer like Si3N4 is used. (C) 2015 American Vacuum Society.

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.

Paths Towards High Efficiency Silicon Photovoltaics

While photovoltaics hold much promise as a sustainable electricity source, continued cost reduction is necessary to continue the current growth in deployment. A promising path to continuing to reduce total system cost is by increasing device efficiency. This thesis explores several silicon-based photovoltaic technologies with the potential to reach high power conversion efficiencies. Silicon microwire arrays, formed by joining millions of micron diameter wires together, were developed as a low cost, low efficiency solar technology. The feasibility of transitioning this to a high efficiency technology was explored. In order to achieve high efficiency, high quality silicon material must be used. Lifetimes and diffusion lengths in these wires were measured and the action of various surface passivation treatments studied. While long lifetimes were not achieved, strong inversion at the silicon / hydrofluoric acid interface was measured, which is important for understanding a common measurement used in solar materials characterization.

Cryogenic deep reactive ion etching was then explored as a method for fabricating high quality wires and improved lifetimes were measured. As another way to reach high efficiency, growth of silicon-germanium alloy wires was explored as a substrate for a III-V on Si tandem device. Patterned arrays of wires with up to 12% germanium incorporation were grown. This alloy is more closely lattice matched to GaP than silicon and allows for improvements in III-V integration on silicon.

Heterojunctions of silicon are another promising path towards achieving high efficiency devices. The GaP/Si heterointerface and properties of GaP grown on silicon were studied. Additionally, a substrate removal process was developed which allows the formation of high quality free standing GaP films and has wide applications in the field of optics.

Finally, the effect of defects at the interface of the amorphous silicon heterojuction cell was studied. Excellent voltages, and thus efficiencies, are achievable with this system, but the voltage is very sensitive to growth conditions. We directly measured lateral transport lengths at the heterointerface on the order of tens to hundreds of microns, which allows carriers to travel towards any defects that are present and recombine. This measurement adds to the understanding of these types of high efficiency devices and may aid in future device design.

Deep silicon grating as high-extinction-ratio polarizing beam splitter

A deep binary silicon grating as high-extinction-ratio reflective polarizing beam splitter (PBS) at the wavelength of 1550 nm is presented. The design is based on the phenomenon of total internal reflection (TIR) by using the rigorous coupled wave analysis (RCWA). The extinction ratio of the rectangular PBS grating can reach 2.5×105 with the optimum grating period of 397 nm and groove depth of 1.092 μm. The effciencies of TM-polarized wave in the 0th order and TE-polarized wave in the −1st order can both reach unity at the Littrow angle. Holographic recording technology and inductively coupled plasma (ICP) etching could be used to fabricate the silicon PBS grating.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Controllable chemical vapor deposition of large area uniform nanocrystalline graphene directly on silicon dioxide

Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.

Wafer-Level Testable High-Speed Silicon Microring Modulator Integrated with Grating Couplers

A wafer-level testable silicon-on-insulator-based microring modulator is demonstrated with high modulation speed, to which the grating couplers are integrated as the fiber-to-chip interfaces. Cost-efficient fabrications are realized with the help of optical structure and etching depth designs. Grating couplers and waveguides are patterned and etched together with the same slab thickness. Finally we obtain a 3-dB coupling bandwidth of about 60nm and 10 Gb/s nonreturn-to-zero modulation by wafer-level optical and electrical measurements.