A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

On performance of distributed model predictive control in power system frequency regulation

This paper describes the implementation of a distributed model predictive approach for automatic generation control. Performance results are discussed by comparing classical techniques (based on integral control) with model predictive control solutions (centralized and distributed) for different operational scenarios with two interconnected networks. These scenarios include variable load levels (ranging from a small to a large unbalance generated power to power consumption ratio) and simultaneously variable distance between the interconnected networks systems. For the two networks the paper also examines the impact of load variation in an island context (a network isolated from each other).

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Real-Time Tariffs for Electric Vehicles in Wind Power based Power Systems

The use of Electric Vehicles (EVs) will change significantly the planning and management of power systems in a near future. This paper proposes a real-time tariff strategy for the charge process of the EVs. The main objective is to evaluate the influence of real-time tariffs in the EVs owners’ behaviour and also the impact in load diagram. The paper proposes the energy price variation according to the relation between wind generation and power consumption. The proposed strategy was tested in two different days in the Danish power system. January 31st and August 13th 2013 were selected because of the high quantities of wind generation. The main goal is to evaluate the changes in the EVs charging diagram with the energy price preventing wind curtailment.

Verification of analog circuits in power-down mode

Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e Computadores

Switching mode power amplifier for bluetooth applications

Modern fully integrated transceivers architectures, require circuits with low area, low cost, low power, and high efficiency. A key block in modern transceivers is the power amplifier, which is deeply studied in this thesis. First, we study the implementation of a classical Class-A amplifier, describing the basic operation of an RF power amplifier, and analysing the influence of the real models of the reactive components in its operation. Secondly, the Class-E amplifier is deeply studied. The different types of implementations are reviewed and theoretical equations are derived and compared with simulations. There were selected four modes of operation for the Class-E amplifier, in order to perform the implementation of the output stage, and the subsequent comparison of results. This led to the selection of the mode with the best trade-off between efficiency and harmonics distortion, lower power consumption and higher output power. The optimal choice was a parallel circuit containing an inductor with a finite value. To complete the implementation of the PA in switching mode, a driver was implemented. The final block (output stage together with the driver) got 20 % total efficiency (PAE) transmitting 8 dBm output power to a 50 W load with a total harmonic distortion (THD) of 3 % and a total consumption of 28 mW. All implementations are designed using standard 130 nm CMOS technology. The operating frequency is 2.4 GHz and it was considered an 1.2 V DC power supply. The proposed circuit is intended to be used in a Bluetooth transmitter, however, it has a wider range of applications.

Iowa Power Fund Board Project Report Update, July 29, 2009

Amana Farms is using an anaerobic digestion, which is a two-stage digester that converts manure and other organic wastes into three valuable by-products: 1) Biogas – to fuel an engine/generator set to create electricity; 2) Biosolids - used as a livestock bedding material or as a soil amendment; 3) Liquid stream - will be applied as a low-odor fertilizer to growing crops. (see Business Plan appendix H) The methane biogas will be collected from the two stages of the anaerobic digestion vessel and used for fuel in the combined heat and power engine/generator sets. The engine/generator sets are natural gasfueled reciprocating engines modified to burn biogas. The electricity produced by the engine/generator sets will be used to offset on-farm power consumption and the excess power will be sold directly to Amana Society Service Company as a source of green power. The waste heat, in the form of hot water, will be collected from both the engine jacket liquid cooling system and from the engine exhaust (air) system. Approximately 30 to 60% of this waste heat will be used to heat the digester. The remaining waste heat will be used to heat other farm buildings and may provide heat for future use for drying corn or biosolids. The digester effluent will be pumped from the effluent pit at the end of the anaerobic digestion vessel to a manure solids separator. The mechanical manure separator will separate the effluent digested waste stream into solid and liquid fractions. The solids will be dewatered to approximately a 35% solid material. Some of the separated solids will be used by the farm for a livestock bedding replacement. The remaining separated solids may be sold to other farms for livestock bedding purposes or sold to after-markets, such as nurseries and composters for soil amendment material. The liquid from the manure separator, now with the majority of the large solids removed, will be pumped into the farm’s storage lagoon. A significant advantage of the effluent from the anaerobic digestion treatment process is that the viscosity of the effluent is such that the liquid effluent can now be pumped through an irrigation nozzle for field spreading.

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.

The Design and Implementation of a Power Management Feature to a Configuration Management System

Green IT is a term that covers various tasks and concepts that are related to reducing the environmental impact of IT. At enterprise level, Green IT has significant potential to generate sustainable cost savings: the total amount of devices is growing and electricity prices are rising. The lifecycle of a computer can be made more environmentally sustainable using Green IT, e.g. by using energy efficient components and by implementing device power management. The challenge using power management at enterprise level is how to measure and follow-up the impact of power management policies? During the thesis a power management feature was developed to a configuration management system. The feature can be used to automatically power down and power on PCs using a pre-defined schedule and to estimate the total power usage of devices. Measurements indicate that using the feature the device power consumption can be monitored quite precisely and the power consumption can be reduced, which generates electricity cost savings and reduces the environmental impact of IT.

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.

Power efficiency estimation and simulation of different control methods for the rotary screw compressor

Nowadays the energy efficiency has become one of the most concerned topics. Compressors are the equipment, which is very common in industry. Moreover, they tend to operate during long cycles and therefore even small decrease in power consumption can significantly reduce electricity costs during the year. And therefore it is important to investigate ways of increasing the energy efficiency of the compressors. In the thesis rotary screw compressor alongside with different control approaches is described. Simulation models for various control types of rotary screw compressor are developed. Analysis of laboratory equipment is conducted and results are compared with simulation. Suggestions of the real laboratory equipment improvement are given.

Reducing auxiliary power of a fluid bed boiler island

The aim of this thesis is to find and analyze different methods which reduce fluid bed boilers’ auxiliary power consumption. The objective is to examine the effects and feasibility of these methods. The literature part explains how fluid bed boilers work and what are the main sources of auxiliary power consumption. Designs and operation of these equipment are presented. The literature part also discusses the basics of auxiliary power consumption reduction and introduces four low pressure drop constructions. The experimental part inspects six different methods. Effects of these methods on the auxiliary power consumption are calculated and their impacts on the operation of the boiler are modeled. Calculations show that reasonable changes can reduce fluid bed boiler’s auxiliary power consumption by 2,1-10,2 %. Biggest reductions come from lower air coefficients, smaller bed a-level pressures and lower primary/secondary air –ratios. Models showed no problems with the smaller bed a-level pressures. With the lower air coefficients and smaller primary/secondary air –ratios the models showed a significant increase in the carbon monoxide levels.

Power and Performance Management Strategies on NoC-Based Multicore Platforms, Using DVFS, Adaptive Algorithm and Task Parallelism

This work presents synopsis of efficient strategies used in power managements for achieving the most economical power and energy consumption in multicore systems, FPGA and NoC Platforms. In this work, a practical approach was taken, in an effort to validate the significance of the proposed Adaptive Power Management Algorithm (APMA), proposed for system developed, for this thesis project. This system comprise arithmetic and logic unit, up and down counters, adder, state machine and multiplexer. The essence of carrying this project firstly, is to develop a system that will be used for this power management project. Secondly, to perform area and power synopsis of the system on these various scalable technology platforms, UMC 90nm nanotechnology 1.2v, UMC 90nm nanotechnology 1.32v and UMC 0.18 μmNanotechnology 1.80v, in order to examine the difference in area and power consumption of the system on the platforms. Thirdly, to explore various strategies that can be used to reducing system’s power consumption and to propose an adaptive power management algorithm that can be used to reduce the power consumption of the system. The strategies introduced in this work comprise Dynamic Voltage Frequency Scaling (DVFS) and task parallelism. After the system development, it was run on FPGA board, basically NoC Platforms and on these various technology platforms UMC 90nm nanotechnology1.2v, UMC 90nm nanotechnology 1.32v and UMC180 nm nanotechnology 1.80v, the system synthesis was successfully accomplished, the simulated result analysis shows that the system meets all functional requirements, the power consumption and the area utilization were recorded and analyzed in chapter 7 of this work. This work extensively reviewed various strategies for managing power consumption which were quantitative research works by many researchers and companies, it's a mixture of study analysis and experimented lab works, it condensed and presents the whole basic concepts of power management strategy from quality technical papers.

Integrated Management of Interface Power (IMIP) Framework

La présence importante de plusieurs réseaux sans-fils de différentes portées a encouragée le développement d’une nouvelle génération d’équipements portables sans-fils avec plusieurs interfaces radio. Ainsi, les utilisateurs peuvent bénéficier d’une large possibilité de connectivité aux réseaux sans-fils (e.g. Wi-Fi [1], WiMAX [2], 3G [3]) disponibles autour. Cependant, la batterie d’un nœud mobile à plusieurs interfaces sera rapidement épuisée et le temps d’utilisation de l’équipement sera réduit aussi. Pour prolonger l’utilisation du mobile les standards, des réseaux sans-fils, on définie (individuellement) plusieurs états (émission, réception, sleep, idle, etc.); quand une interface radio n’est pas en mode émission/réception il est en mode sleep/idle où la consommation est très faible, comparée aux modes émission/réception. Pourtant, en cas d’équipement portable à multi-interfaces radio, l’énergie totale consommée par les interfaces en mode idle est très importante. Autrement, un équipement portable équipé de plusieurs interfaces radio augmente sa capacité de connectivité mais réduit sa longévité d’utilisation. Pour surpasser cet inconvénient on propose une plate-forme, qu'on appelle IMIP (Integrated Management of Interface Power), basée sur l’extension du standard MIH (Media Independent Handover) IEEE 802.21 [4]. IMIP permet une meilleure gestion d’énergie des interfaces radio, d’un équipement mobile à multi-radio, lorsque celles-ci entrent en mode idle. Les expérimentations que nous avons exécutées montrent que l’utilisation de IMIP permet d'économiser jusqu'a 80% de l'énergie consommée en comparaison avec les standards existants. En effet, IMIP permet de prolonger la durée d'utilisation d'équipements à plusieurs interfaces grâce à sa gestion efficace de l'énergie.

The air distribution index as an indicator for energy consumption and performance of ventilation systems

This paper deals with the energy consumption and the evaluation of the performance of air supply systems for a ventilated room involving high- and low-level supplies. The energy performance assessment is based on the airflow rate, which is related to the fan power consumption by achieving the same environmental quality performance for each case. Four different ventilation systems are considered: wall displacement ventilation, confluent jets ventilation, impinging jet ventilation and a high level mixing ventilation system. The ventilation performance of these systems will be examined by means of achieving the same Air Distribution Index (ADI) for different cases. The widely used high-level supplies require much more fan power than those for low-level supplies for achieving the same value of ADI. In addition, the supply velocity, hence the supply dynamic pressure, for a high-level supply is much larger than for low-level supplies. This further increases the power consumption for high-level supply systems. The paper considers these factors and attempts to provide some guidelines on the difference in the energy consumption associated with high and low level air supply systems. This will be useful information for designers and to the authors' knowledge there is a lack of information available in the literature on this area of room air distribution. The energy performance of the above-mentioned ventilation systems has been evaluated on the basis of the fan power consumed which is related to the airflow rate required to provide equivalent indoor environment. The Air Distribution Index (ADI) is used to evaluate the indoor environment produced in the room by the ventilation strategy being used. The results reveal that mixing ventilation requires the highest fan power and the confluent jets ventilation needs the lowest fan power in order to achieve nearly the same value of ADI.