834 resultados para parallel operation


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Dual frequency operation is achieved from a compact microstrip antenna by loading a pair of narrow slots close to its radiating edges. The two frequencies have parallel polarization planes and similar radiation characteristics. The ratio between the two operating frequencies can be tuned in the range (1.14-1. 24), which is much smaller than that of similar designs. The above excellent radiation characteristics are achieved along with an area reduction of - 75% compared to the standard rectangular patch

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This report addresses the problem of acquiring objects using articulated robotic hands. Standard grasps are used to make the problem tractable, and a technique is developed for generalizing these standard grasps to increase their flexibility to variations in the problem geometry. A generalized grasp description is applied to a new problem situation using a parallel search through hand configuration space, and the result of this operation is a global overview of the space of good solutions. The techniques presented in this report have been implemented, and the results are verified using the Salisbury three-finger robotic hand.

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Scheduling tasks to efficiently use the available processor resources is crucial to minimizing the runtime of applications on shared-memory parallel processors. One factor that contributes to poor processor utilization is the idle time caused by long latency operations, such as remote memory references or processor synchronization operations. One way of tolerating this latency is to use a processor with multiple hardware contexts that can rapidly switch to executing another thread of computation whenever a long latency operation occurs, thus increasing processor utilization by overlapping computation with communication. Although multiple contexts are effective for tolerating latency, this effectiveness can be limited by memory and network bandwidth, by cache interference effects among the multiple contexts, and by critical tasks sharing processor resources with less critical tasks. This thesis presents techniques that increase the effectiveness of multiple contexts by intelligently scheduling threads to make more efficient use of processor pipeline, bandwidth, and cache resources. This thesis proposes thread prioritization as a fundamental mechanism for directing the thread schedule on a multiple-context processor. A priority is assigned to each thread either statically or dynamically and is used by the thread scheduler to decide which threads to load in the contexts, and to decide which context to switch to on a context switch. We develop a multiple-context model that integrates both cache and network effects, and shows how thread prioritization can both maintain high processor utilization, and limit increases in critical path runtime caused by multithreading. The model also shows that in order to be effective in bandwidth limited applications, thread prioritization must be extended to prioritize memory requests. We show how simple hardware can prioritize the running of threads in the multiple contexts, and the issuing of requests to both the local memory and the network. Simulation experiments show how thread prioritization is used in a variety of applications. Thread prioritization can improve the performance of synchronization primitives by minimizing the number of processor cycles wasted in spinning and devoting more cycles to critical threads. Thread prioritization can be used in combination with other techniques to improve cache performance and minimize cache interference between different working sets in the cache. For applications that are critical path limited, thread prioritization can improve performance by allowing processor resources to be devoted preferentially to critical threads. These experimental results show that thread prioritization is a mechanism that can be used to implement a wide range of scheduling policies.

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A key capability of data-race detectors is to determine whether one thread executes logically in parallel with another or whether the threads must operate in series. This paper provides two algorithms, one serial and one parallel, to maintain series-parallel (SP) relationships "on the fly" for fork-join multithreaded programs. The serial SP-order algorithm runs in O(1) amortized time per operation. In contrast, the previously best algorithm requires a time per operation that is proportional to Tarjan’s functional inverse of Ackermann’s function. SP-order employs an order-maintenance data structure that allows us to implement a more efficient "English-Hebrew" labeling scheme than was used in earlier race detectors, which immediately yields an improved determinacy-race detector. In particular, any fork-join program running in T₁ time on a single processor can be checked on the fly for determinacy races in O(T₁) time. Corresponding improved bounds can also be obtained for more sophisticated data-race detectors, for example, those that use locks. By combining SP-order with Feng and Leiserson’s serial SP-bags algorithm, we obtain a parallel SP-maintenance algorithm, called SP-hybrid. Suppose that a fork-join program has n threads, T₁ work, and a critical-path length of T[subscript ∞]. When executed on P processors, we prove that SP-hybrid runs in O((T₁/P + PT[subscript ∞]) lg n) expected time. To understand this bound, consider that the original program obtains linear speed-up over a 1-processor execution when P = O(T₁/T[subscript ∞]). In contrast, SP-hybrid obtains linear speed-up when P = O(√T₁/T[subscript ∞]), but the work is increased by a factor of O(lg n).

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This paper presents the research and development of a 3-legged micro Parallel Kinematic Manipulator (PKM) for positioning in micro-machining and assembly operations. The structural characteristics associated with parallel manipulators are evaluated and the PKMs with translational and rotational movements are identified. Based on these identifications, a hybrid 3-UPU (Universal Joint-Prismatic Joint-Universal Joint) parallel manipulator is designed and fabricated. The principles of the operation and modeling of this micro PKM is largely similar to a normal size Stewart Platform (SP). A modular design methodology is introduced for the construction of this micro PKM. Calibration results of this hybrid 3-UPU PKM are discussed in this paper.

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The sampling of certain solid angle is a fundamental operation in realistic image synthesis, where the rendering equation describing the light propagation in closed domains is solved. Monte Carlo methods for solving the rendering equation use sampling of the solid angle subtended by unit hemisphere or unit sphere in order to perform the numerical integration of the rendering equation. In this work we consider the problem for generation of uniformly distributed random samples over hemisphere and sphere. Our aim is to construct and study the parallel sampling scheme for hemisphere and sphere. First we apply the symmetry property for partitioning of hemisphere and sphere. The domain of solid angle subtended by a hemisphere is divided into a number of equal sub-domains. Each sub-domain represents solid angle subtended by orthogonal spherical triangle with fixed vertices and computable parameters. Then we introduce two new algorithms for sampling of orthogonal spherical triangles. Both algorithms are based on a transformation of the unit square. Similarly to the Arvo's algorithm for sampling of arbitrary spherical triangle the suggested algorithms accommodate the stratified sampling. We derive the necessary transformations for the algorithms. The first sampling algorithm generates a sample by mapping of the unit square onto orthogonal spherical triangle. The second algorithm directly compute the unit radius vector of a sampling point inside to the orthogonal spherical triangle. The sampling of total hemisphere and sphere is performed in parallel for all sub-domains simultaneously by using the symmetry property of partitioning. The applicability of the corresponding parallel sampling scheme for Monte Carlo and Quasi-D/lonte Carlo solving of rendering equation is discussed.

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As consumers demand more functionality) from their electronic devices and manufacturers supply the demand then electrical power and clock requirements tend to increase, however reassessing system architecture can fortunately lead to suitable counter reductions. To maintain low clock rates and therefore reduce electrical power, this paper presents a parallel convolutional coder for the transmit side in many wireless consumer devices. The coder accepts a parallel data input and directly computes punctured convolutional codes without the need for a separate puncturing operation while the coded bits are available at the output of the coder in a parallel fashion. Also as the computation is in parallel then the coder can be clocked at 7 times slower than the conventional shift-register based convolutional coder (using DVB 7/8 rate). The presented coder is directly relevant to the design of modern low-power consumer devices

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Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

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Exascale systems are the next frontier in high-performance computing and are expected to deliver a performance of the order of 10^18 operations per second using massive multicore processors. Very large- and extreme-scale parallel systems pose critical algorithmic challenges, especially related to concurrency, locality and the need to avoid global communication patterns. This work investigates a novel protocol for dynamic group communication that can be used to remove the global communication requirement and to reduce the communication cost in parallel formulations of iterative data mining algorithms. The protocol is used to provide a communication-efficient parallel formulation of the k-means algorithm for cluster analysis. The approach is based on a collective communication operation for dynamic groups of processes and exploits non-uniform data distributions. Non-uniform data distributions can be either found in real-world distributed applications or induced by means of multidimensional binary search trees. The analysis of the proposed dynamic group communication protocol has shown that it does not introduce significant communication overhead. The parallel clustering algorithm has also been extended to accommodate an approximation error, which allows a further reduction of the communication costs. The effectiveness of the exact and approximate methods has been tested in a parallel computing system with 64 processors and in simulations with 1024 processing elements.

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Global communication requirements and load imbalance of some parallel data mining algorithms are the major obstacles to exploit the computational power of large-scale systems. This work investigates how non-uniform data distributions can be exploited to remove the global communication requirement and to reduce the communication cost in iterative parallel data mining algorithms. In particular, the analysis focuses on one of the most influential and popular data mining methods, the k-means algorithm for cluster analysis. The straightforward parallel formulation of the k-means algorithm requires a global reduction operation at each iteration step, which hinders its scalability. This work studies a different parallel formulation of the algorithm where the requirement of global communication can be relaxed while still providing the exact solution of the centralised k-means algorithm. The proposed approach exploits a non-uniform data distribution which can be either found in real world distributed applications or can be induced by means of multi-dimensional binary search trees. The approach can also be extended to accommodate an approximation error which allows a further reduction of the communication costs.

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A novel cryptography method based on the Lorenz`s attractor chaotic system is presented. The proposed algorithm is secure and fast, making it practical for general use. We introduce the chaotic operation mode, which provides an interaction among the password, message and a chaotic system. It ensures that the algorithm yields a secure codification, even if the nature of the chaotic system is known. The algorithm has been implemented in two versions: one sequential and slow and the other, parallel and fast. Our algorithm assures the integrity of the ciphertext (we know if it has been altered, which is not assured by traditional algorithms) and consequently its authenticity. Numerical experiments are presented, discussed and show the behavior of the method in terms of security and performance. The fast version of the algorithm has a performance comparable to AES, a popular cryptography program used commercially nowadays, but it is more secure, which makes it immediately suitable for general purpose cryptography applications. An internet page has been set up, which enables the readers to test the algorithm and also to try to break into the cipher.

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In 1977, when teacher education inSwedenwas incorporated into the university system, the main reason was to transform it into an academic tradition. Now, nearly 30 years later, there is still tension between the academic and the vocational tradition; they show up as different and separated elements in a program that is meant to prepare students for a career as a teacher and for a possible future career as a researcher in this field. This tension gives rise to a risk of allowing parallel “tracks” to develop and of isolating the degree thesis work from other courses. On the teacher-training program in which we are involved, close co-operation with partner-schools, where the practical part of the program takes place, has been established. Here, the students´ degree theses are an important factor in making this co-operation work on a concrete level. Accordingly, the purpose of the degree thesis is both to reflect problems in schools and contribute to better teaching in the individual school, but also to offer relevant educational subject matter to the students, which may be adapted as an element in the university’s research environments. From these points of view, the degree thesis is an important part of teacher education and rather more than just a single course. The degree thesis should be an element that gives the students an opportunity to show that they have reached central goals in the teacher education program. It should also be an integral part in the development of critical and scholarly thinking, deepening pedagogical and didactic knowledge and giving the students an opportunity to apply research methods. We will here use two minor case studies: one that compares teacher education programs in five Swedish universities and one minor study at one of those universities, in order to elaborate on the questions: - What purpose has a degree thesis and what role does it play in teacher education? - What criteria are relevant to assessing a degree thesis and what qualities do the degree theses have? - Is it possible to assess a degree thesis fairly and what happens to students who do not pass? - How could the degree thesis be used to improve the contact between the teacher education program and its partner schools in order to contribute to the development of the individual school?

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This paper presents a new methodology for the adjustment of the preheating process and steady-state operation of electronic ballasts intended for hot-cathode fluorescent lamps. The classical series-resonant parallel-loaded half-bridge inverter is the power stage analyzed in this paper. In addition, the preheating process is based on the imposition of a constant rms current through the electrodes, in order to provide a proper value of the R-h/R-c ratio before the lamp start. According to the proposed methodology, it is possible to set suitable operating points for, the electronic ballast, considering optimal conditions for the lamps electrodes. Therefore, the proposed methodology for setting the preheating and steady-state operation is a complete platform to the design of electronic ballasts for hot-cathode fluorescent lamps.

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The analysis of alcoholic beverages for the important carcinogenic contaminant ethyl carbamate is very time-consuming and expensive. Due to possible matrix interferences, sample cleanup using diatomaceous earth (Extrelut) column is required prior to gas chromatographic and mass spectrometric measurement. A limiting step in this process is the rotary evaporation of the eluate containing the analyte in organic solvents, which is currently conducted manually and requires approximately 20-30 min per sample. This paper introduces the use of a parallel evaporation device for ethyl carbamate analysis, which allows for the simultaneous evaporation of 12 samples to a specified residual volume without manual intervention. A more efficient and, less expensive analysis is therefore possible. The method validation showed no differences between the fully-automated parallel evaporation and the manual operation. The applicability was proven by analyzing authentic spirit samples from Germany, Canada and Brazil. It is interesting to note that Brazilian cachacas had a relatively high incidence for ethyl carbamate contamination (55% of all samples were above 0.15 mg/l), which may be of public health relevance and requires further evaluation.

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This paper presents a new methodology for the determination of fluorescent lamp models based on equivalent resistances. One important feature of the proposed methodology is concerned with the inclusion of the filaments into the model, considering the effects of dimming operation on the equivalent resistances. The classical Series-Resonant Parallel-Loaded Half-Bridge inverter is used as the power stage of the ballast. Moreover, the variation of the inverter's switching frequency is the dimming technique assumed for the analyses. Results obtained with a F32T8 lamp indicate that the accuracy of the model is very satisfactory. Thus, the lamp models obtained with the proposed methodology have the potential to serve as an important tool for ballast designers, considering the necessity for evaluating the lamp/ballast compatibility, according to issues concerned to the operating conditions of the electrodes' filaments.