985 resultados para math.DG
Resumo:
A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.
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Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.
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In today's API-rich world, programmer productivity depends heavily on the programmer's ability to discover the required APIs. In this paper, we present a technique and tool, called MATHFINDER, to discover APIs for mathematical computations by mining unit tests of API methods. Given a math expression, MATHFINDER synthesizes pseudo-code to compute the expression by mapping its subexpressions to API method calls. For each subexpression, MATHFINDER searches for a method such that there is a mapping between method inputs and variables of the subexpression. The subexpression, when evaluated on the test inputs of the method under this mapping, should produce results that match the method output on a large number of tests. We implemented MATHFINDER as an Eclipse plugin for discovery of third-party Java APIs and performed a user study to evaluate its effectiveness. In the study, the use of MATHFINDER resulted in a 2x improvement in programmer productivity. In 96% of the subexpressions queried for in the study, MATHFINDER retrieved the desired API methods as the top-most result. The top-most pseudo-code snippet to implement the entire expression was correct in 93% of the cases. Since the number of methods and unit tests to mine could be large in practice, we also implement MATHFINDER in a MapReduce framework and evaluate its scalability and response time.
Resumo:
Today's programming languages are supported by powerful third-party APIs. For a given application domain, it is common to have many competing APIs that provide similar functionality. Programmer productivity therefore depends heavily on the programmer's ability to discover suitable APIs both during an initial coding phase, as well as during software maintenance. The aim of this work is to support the discovery and migration of math APIs. Math APIs are at the heart of many application domains ranging from machine learning to scientific computations. Our approach, called MATHFINDER, combines executable specifications of mathematical computations with unit tests (operational specifications) of API methods. Given a math expression, MATHFINDER synthesizes pseudo-code comprised of API methods to compute the expression by mining unit tests of the API methods. We present a sequential version of our unit test mining algorithm and also design a more scalable data-parallel version. We perform extensive evaluation of MATHFINDER (1) for API discovery, where math algorithms are to be implemented from scratch and (2) for API migration, where client programs utilizing a math API are to be migrated to another API. We evaluated the precision and recall of MATHFINDER on a diverse collection of math expressions, culled from algorithms used in a wide range of application areas such as control systems and structural dynamics. In a user study to evaluate the productivity gains obtained by using MATHFINDER for API discovery, the programmers who used MATHFINDER finished their programming tasks twice as fast as their counterparts who used the usual techniques like web and code search, IDE code completion, and manual inspection of library documentation. For the problem of API migration, as a case study, we used MATHFINDER to migrate Weka, a popular machine learning library. Overall, our evaluation shows that MATHFINDER is easy to use, provides highly precise results across several math APIs and application domains even with a small number of unit tests per method, and scales to large collections of unit tests.
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本文介绍一种0~10mm、分辨率1μm数字光栅测微仪,它是一种具有任意零点、高精度的测长系统,由光栅位移传感器和数显仪两部分组成。介绍了其工作原理、主要技术指标和应用。
Resumo:
<正> 由中国科学院力学研究所研制的DG-10数显光栅测微仪,经中国计量科学研究院检定,其主要技术指标: 1.量程0-10mm;2.分度值0.001mm;3.示值误差在全量程内为±0.001mm;4.回程误差0.001mm;5.测杆受径向力作用时示值变化0.001mm。
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中国科学院近代物理研究所成功研制了DG系列中频变压器型工业电子加速器,其中DG-2.5型加速器能量范围1.0–2.5MeV,最大束流功率90kW,束流扫描有效宽度1000mm,适用于各种辐照领域;DG-1.2型能量范围0.8–1.2MeV,最大功率50kW;这两种型号加速器均通过了长时间测试,工作稳定、故障率低,采用计算机自动控制,并可与束下传动系统连锁,完全达到了工业应用的标准。
Resumo:
生物多样性通常使用物种丰富度、Simpson指数、Shannon-Wiener多样性指数等来进行度量,但是在土壤动物群落研究中,由于使用了粗水平的分类方法,因此即使生境变化很大,这些多样性指数在评估群落多样性变化时仍然是不适当的。为了克服这种限制,廖崇惠(1990,2009)提出用DG指数来代替这些标准的多样性指数,并在土壤动物生态学领域得到了广泛应用。然而笔者分析发现DG指数与Pielou均匀度指数呈显著的负相关关系(r=–0.534,P=0.000),即,高的均匀度反而有低的多样性。另外,DG指数与类群数(r=0.648,P=0.000)和类群密度(r=0.487,P=0.000)呈明显的正相关,类群数的下降可以通过部分类群密度的上升而获得补偿,群落的类群丢失后却可以获得一个不变的甚至更高的多样性值。因此,笔者不支持DG指数用于测度生物多样性,提议使用各类群实际群势与潜在群势比值的平均值来估计群落潜在多度的实现程度。如果继续使用DG指数作为实际生境条件的一个指标,那么与以往不同,DG指数测度的是该生境群落多度增长的一种潜力。
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Math-Towers (www.math-towers.ca) is a collaborative mathematics environment for pupils in grades 7 to 9. Using a fantasy adventure game context students are presented with a mathematical challenge, given online tools for working on the problem,and provided with a messaging system by which they may exchange ideas and partial solutions. This paper presents the philosophy behind the design of Math-Towers and work with students that indicates the extent to which we have been successful in meeting our aims. The technical and social problems encountered and revisions made to address these are also described.
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Math-Towers (www.math-towers.ca) is an online resource for students in grades 6 to 10 that supports collaborative problem-solving and investigations. This paper presents the philosophical position motivating the development of Math-Towers and describes how the site presents and motivates the mathematical challenges and supports participants' exploration and collaboration.
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Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.
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In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.
Resumo:
A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.
Resumo:
Given that the ability to manage numbers is essential in a modern society, mathematics anxiety – which has been demonstrated to have unfortunate consequences in terms of mastery of math – has become a subject of increasing interest, and the need to accurately measure it has arisen. One of the widely employed scales to measure math anxiety is the Abbreviated Math Anxiety Scale (AMAS) (Hopko, Mahadevan, Bare & Hunt, 2003). The first aim of the present paper was to confirm the factor structure of the AMAS when administered to Italian high school and college students, and to test the invariance of the scale across educational levels. Additionally, we assessed the reliability and validity of the Italian version of the scale. Finally, we tested the invariance of the AMAS across genders. The overall findings provide evidence for the validity and reliability of the AMAS when administered to Italian students.