Analysis and performance assessment of 6-pulse inverter-fed 3-phase and 6-phase induction machines

The paper describes a model for a 6-phase induction motor driven by an inverter operating in a 6-pulse (square wave) mode. The model is implemented and performance, in terms of torque, current, efficiency and pulsating torque, compared to the performance of a 3-phase motor (both sine and 6-pulse supplied). The models are verified experimentally, in particular the efficiency performance, and it is illustrated that the improvement in inverter efficiency when in 6-pulse operating mode may improve the performance of the overall system. © 2005 IEEE.

Performance assessment of XACML authorizations for supply chain traceability web services

Service-Oriented Architecture (SOA) and Web Services (WS) offer advanced flexibility and interoperability capabilities. However they imply significant performance overheads that need to be carefully considered. Supply Chain Management (SCM) and Traceability systems are an interesting domain for the use of WS technologies that are usually deemed to be too complex and unnecessary in practical applications, especially regarding security. This paper presents an externalized security architecture that uses the eXtensible Access Control Markup Language (XACML) authorization standard to enforce visibility restrictions on trace-ability data in a supply chain where multiple companies collaborate; the performance overheads are assessed by comparing 'raw' authorization implementations - Access Control Lists, Tokens, and RDF Assertions - with their XACML-equivalents. © 2012 IEEE.

Reflections on the development of a dynamic learning, teaching and assessment strategy.

Developing learning, teaching and assessment strategies that foster ongoing engagement and provide inspiration to academic staff is a particular challenge. This paper demonstrates how an institutional learning, teaching and assessment strategy was developed and a ‘dynamic’ strategy created in order to achieve the ongoing enhancement of the quality of the student learning experience. The authors use the discussion of the evolution, development and launch of the Strategy and underpinning Resource Bank to reflect on the hopes and intentions behind the approach; firstly the paper will discuss the collaborative and iterative approach taken to the development of an institutional learning, teaching and assessment strategy; and secondly, the development of open access educational resources to underpin the strategy. The paper then outlines staff engagement with the resource bank and positive outcomes which have been identified to date, identifies the next steps in achieving the ambition behind the strategy and outlines the action research and fuller evaluation which will be used to monitor progress and ensure responsive learning at institutional level.

A survey of teaching and assessment methods employed in UK higher education programmes for HCI course

A survey of teaching and assessment methods employed in UK Higher Education programmes for Human-Computer Interaction (HCI) courses was conducted in April 2003. The findings from this survey are presented, and conclusions drawn.

Performance assessment in serious games: Compensating for the effects of randomness

This paper is about performance assessment in serious games. We conceive serious gaming as a process of player-lead decision taking. Starting from combinatorics and item-response theory we provide an analytical model that makes explicit to what extent observed player performances (decisions) are blurred by chance processes (guessing behaviors). We found large effects both theoretically and practically. In two existing serious games random guess scores were found to explain up to 41% of total scores. Monte Carlo simulation of random game play confirmed the substantial impact of randomness on performance. For valid performance assessments, be it in-game or post-game, the effects of randomness should be included to produce re-calibrated scores that can reasonably be interpreted as the players´ achievements.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.