On-line Estimation of Fundamental and Ripple Components of Line Currents in a Voltage-Source Inverter Operated at Low Switching Frequency

High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

Evaluation and Minimization of Low-Order Harmonic Torque in Low-Switching-Frequency Inverter-Fed Induction Motor Drives

A low-order harmonic pulsating torque is a major concern in high-power drives, high-speed drives, and motor drives operating in an overmodulation region. This paper attempts to minimize the low-order harmonic torques in induction motor drives, operated at a low pulse number (i.e., a low ratio of switching frequency to fundamental frequency), through a frequency domain (FD) approach as well as a synchronous reference frame (SRF) based approach. This paper first investigates FD-based approximate elimination of harmonic torque as suggested by classical works. This is then extended into a procedure for minimization of low-order pulsating torque components in the FD, which is independent of machine parameters and mechanical load. Furthermore, an SRF-based optimal pulse width modulation (PWM) method is proposed to minimize the low-order harmonic torques, considering the motor parameters and load torque. The two optimal methods are evaluated and compared with sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experimental studies on a 3.7-kW induction motor drive. The SRF-based optimal PWM results in marginally better performance than the FD-based one. However, the selection of optimal switching angle for any modulation index (M) takes much longer in case of SRF than in case of the FD-based approach. The FD-based optimal solutions can be used as good starting solutions and/or to reasonably restrict the search space for optimal solutions in the SRF-based approach. Both of the FD-based and SRF-based optimal PWM methods reduce the low-order pulsating torque significantly, compared to ST PWM and SHE PWM, as shown by the simulation and experimental results.

Starting slow: the effects of response-switching frequency on patterns of cardiovascular reactivity

Research findings suggest that switching between competing response sets can be resource demanding. The current study focused on concurrent health-relevant physiological effects of task switching by assessing cardiovascular response at varying levels of switch frequency. The participants performed a response-switching task at three different levels of response set switching frequency (low, medium and high) while measurements of blood pressure and heart rate were taken. One group was exposed to response-switching frequency conditions in the order low → medium → high, while the other group was exposed to the same task conditions in the reverse order (i.e. high → medium → low). The results showed that the participants in the low → medium → high switch frequency group recovered faster from initially heightened systolic blood pressure when compared with participants in the high → medium → low group. It is concluded that the results point to a physiological "carry over" effect associated with beginning a task at rapid response switching frequency levels, and suggest the importance of habituation to task demands as a means of offsetting potentially unhealthy levels of reactivity. Implications for modern work environments are discussed.

Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.

A high frequency, low voltage stackable full bridge module for modular multilevel cascade converter (MMCC) research

A new small full bridge module for MMCC research is presented. Each full bridge converter cell is a single small (65 × 30 mm) multilayer PCB with two low voltage high current (22 V, 40 A) integrated half bridge ICs and the necessary isolated control signals and auxiliary power supply (2500 V isolation). All devices are surface mount, minimising cell height (4 mm) and parasitic inductance. Each converter cell can be physically stacked with PCB connectors propagating the control signals and inter-cell power connections. Many cells can be trivially stacked to create a large multilevel converter leg with isolated auxiliary power and control signals. Any of the MMCC family members is then easily formed. With a change in placement of stacking connector, a parallel connection of bridges is also possible. Operation of a nine level parallel full bridge is demonstrated at 12 V and 384 kHz switching frequency delivering a 30 W 2 kHz sinewave into a resistive load. A number of new applications for this novel module aside from MMCC development are listed.

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for Reduced Harmonic Distortion and Switching Loss

Novel switching sequences can be employed in spacevector-based pulsewidth modulation (PWM) of voltage source inverters. Differentswitching sequences are evaluated and compared in terms of inverter switching loss. A hybrid PWM technique named minimum switching loss PWM is proposed, which reduces the inverter switching loss compared to conventional space vector PWM (CSVPWM) and discontinuous PWM techniques at a given average switching frequency. Further, four space-vector-based hybrid PWM techniques are proposed that reduce line current distortion as well as switching loss in motor drives, compared to CSVPWM. Theoretical and experimental results are presented.

Novel Switching Sequences for a Space-Vector-Modulated Three-Level Inverter

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors.The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation(PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion(THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Analytical Closed-Form Expressions for Harmonic Distortion Corresponding to Novel Switching Sequences for Neutral-Point-Clamped Inverters

Analytical closed-form expressions for harmonic distortion factors corresponding to various pulsewidth modulation (PWM) techniques for a two-level inverter have been reported in the literature. This paper derives such analytical closed-form expressions, pertaining to centered space-vector PWM (CSVPWM) and eight different advanced bus-clamping PWM (ABCPWM) schemes, for a three-level neutral-point-clamped (NPC) inverter. These ABCPWM schemes switch each phase at twice the nominal switching frequency in certain intervals of the line cycle while clamping each phase to one of the dc terminals over certain other intervals. The harmonic spectra of the output voltages, corresponding to the eight ABCPWM schemes, are studied and compared experimentally with that of CSVPWM over the entire modulation range. The measured values of weighted total harmonic distortion (WTHD) of the line voltage V-WTHD are used to validate the analytical closed-form expressions derived. The analytical expressions, pertaining to two of the ABCPWM methods, are also validated by measuring the total harmonic distortion (THD) in the line current I-THD on a 2.2-kW constant volts-per-hertz induction motor drive.

A delay model for noise-induced bi-directional switching

Many biological systems can switch between two distinct states. Once switched, the system remains stable for a period of time and may switch back to its original state. A gene network with bistability is usually required for the switching and stochastic effect in the gene expression may induce such switching. A typical bistable system allows one-directional switching, in which the switch from the low state to the high state or from the high state to the low state occurs under different conditions. It is usually difficult to enable bi-directional switching such that the two switches can occur under the same condition. Here, we present a model consisting of standard positive feedback loops and an extra negative feedback loop with a time delay to study its capability to produce bi-directional switching induced by noise. We find that the time delay in the negative feedback is critical for robust bi-directional switching and the length of delay affects its switching frequency.

Influence of voltage and frequency dimming on power losses in HF electronic ballasts for compact fluorescent lamps

Compact Fluorescent Lamps (CFL) incorporating electronic ballasts are widely used in lighting. In many cases the ability to dim the lamp is a requirement Dimming can be achieved by varying the voltage supplied to the inverter or by changing the switching frequency of the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in PSPICE, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. The model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2006 IEEE.

Influence of voltage and frequency dimming on power losses in hf electronic ballasts for compact fluorescent lamps

Compact fluorescent lamps (CFLs) incorporating electronic ballasts are widely used in lighting. In many cases, the ability to dim the lamp is a requirement. Dimming can be achieved by varying the switching frequency of the inverter or by changing the voltage supplied to the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in Pspice, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. After verification, the model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2011 IEEE.

Optimal inverter design for an induction machine using resonant frequency matching

The frequency responses of two 50 Hz and one 400 Hz induction machines have been measured experimentally over a frequency range of 1 kHz to 400 kHz. This study has shown that the stator impedances of the machines behave in a similar manner to a parallel resonant circuit, and hence have a resonant point at which the Input impedance of the machine is at a maximum. This maximum impedance point was found experimentally to be as low as 33 kHz, which is well within the switching frequency ranges of modern inverter drives. This paper investigates the possibility of exploiting the maximum impedance point of the machine, by taking it into consideration when designing an inverter, in order to minimize ripple currents due to the switching frequency. Minimization of the ripple currents would reduce torque pulsation and losses, increasing overall performance. A modified machine model was developed to take into account the resonant point, and this model was then simulated with an inverter to demonstrate the possible advantages of matching the inverter switching frequency to the resonant point. Finally, in order to experimentally verify the simulated results, a real inverter with a variable switching frequency was used to drive an induction machine. Experimental results are presented.

Effects of dense code-switching on executive control

Bilingualism is reported to re-structure executive control networks, but it remains unknown which aspects of the bilingual experience cause this modulation. This study explores the impact of three code-switching types on executive functions: (1) alternation of languages, (2) insertion of lexicon of one language into grammar of another, (3) dense code-switching with co-activation of lexicon and grammar. Current models hypothesise that they challenge different aspects of the executive system because they vary in the extent and scope of language separation. Two groups of German-English bilinguals differing in dense code-switching frequency participated in a flanker task under conditions varying in degree of trial-mixing and resulting demands to conflict-monitoring. Bilinguals engaging in more dense code-switching showed inhibitory advantages in the condition requiring most conflict-monitoring. Moreover, dense code-switching frequency correlated positively with monitoring skills. This suggests that the management of co-activated languages during dense code-switching engages conflict-monitoring and that the consolidation processes taking place within co-activated linguistic systems involve local inhibition. Code-switching types requiring greater degrees of language separation may involve more global forms of inhibition. This study shows that dense code-switching is a key experience shaping bilinguals’ executive functioning and highlights the importance of controlling for participants’ code-switching habits in bilingualism research.