TCAD approaches to multidimensional simulation of advanced semiconductor devices

Technology scaling increasingly emphasizes complexity and non-ideality of the electrical behavior of semiconductor devices and boosts interest on alternatives to the conventional planar MOSFET architecture. TCAD simulation tools are fundamental to the analysis and development of new technology generations. However, the increasing device complexity is reflected in an augmented dimensionality of the problems to be solved. The trade-off between accuracy and computational cost of the simulation is especially influenced by domain discretization: mesh generation is therefore one of the most critical steps and automatic approaches are sought. Moreover, the problem size is further increased by process variations, calling for a statistical representation of the single device through an ensemble of microscopically different instances. The aim of this thesis is to present multi-disciplinary approaches to handle this increasing problem dimensionality in a numerical simulation perspective. The topic of mesh generation is tackled by presenting a new Wavelet-based Adaptive Method (WAM) for the automatic refinement of 2D and 3D domain discretizations. Multiresolution techniques and efficient signal processing algorithms are exploited to increase grid resolution in the domain regions where relevant physical phenomena take place. Moreover, the grid is dynamically adapted to follow solution changes produced by bias variations and quality criteria are imposed on the produced meshes. The further dimensionality increase due to variability in extremely scaled devices is considered with reference to two increasingly critical phenomena, namely line-edge roughness (LER) and random dopant fluctuations (RD). The impact of such phenomena on FinFET devices, which represent a promising alternative to planar CMOS technology, is estimated through 2D and 3D TCAD simulations and statistical tools, taking into account matching performance of single devices as well as basic circuit blocks such as SRAMs. Several process options are compared, including resist- and spacer-defined fin patterning as well as different doping profile definitions. Combining statistical simulations with experimental data, potentialities and shortcomings of the FinFET architecture are analyzed and useful design guidelines are provided, which boost feasibility of this technology for mainstream applications in sub-45 nm generation integrated circuits.

Numerical simulation of interdigitated back contact hetero-junction solar cells

The goal of this thesis is the application of an opto-electronic numerical simulation to heterojunction silicon solar cells featuring an all back contact architecture (Interdigitated Back Contact Hetero-Junction IBC-HJ). The studied structure exhibits both metal contacts, emitter and base, at the back surface of the cell with the objective to reduce the optical losses due to the shadowing by front contact of conventional photovoltaic devices. Overall, IBC-HJ are promising low-cost alternatives to monocrystalline wafer-based solar cells featuring front and back contact schemes, in fact, for IBC-HJ the high concentration doping diffusions are replaced by low-temperature deposition processes of thin amorphous silicon layers. Furthermore, another advantage of IBC solar cells with reference to conventional architectures is the possibility to enable a low-cost assembling of photovoltaic modules, being all contacts on the same side. A preliminary extensive literature survey has been helpful to highlight the specific critical aspects of IBC-HJ solar cells as well as the state-of-the-art of their modeling, processing and performance of practical devices. In order to perform the analysis of IBC-HJ devices, a two-dimensional (2-D) numerical simulation flow has been set up. A commercial device simulator based on finite-difference method to solve numerically the whole set of equations governing the electrical transport in semiconductor materials (Sentuarus Device by Synopsys) has been adopted. The first activity carried out during this work has been the definition of a 2-D geometry corresponding to the simulation domain and the specification of the electrical and optical properties of materials. In order to calculate the main figures of merit of the investigated solar cells, the spatially resolved photon absorption rate map has been calculated by means of an optical simulator. Optical simulations have been performed by using two different methods depending upon the geometrical features of the front interface of the solar cell: the transfer matrix method (TMM) and the raytracing (RT). The first method allows to model light prop-agation by plane waves within one-dimensional spatial domains under the assumption of devices exhibiting stacks of parallel layers with planar interfaces. In addition, TMM is suitable for the simulation of thin multi-layer anti reflection coating layers for the reduction of the amount of reflected light at the front interface. Raytracing is required for three-dimensional optical simulations of upright pyramidal textured surfaces which are widely adopted to significantly reduce the reflection at the front surface. The optical generation profiles are interpolated onto the electrical grid adopted by the device simulator which solves the carriers transport equations coupled with Poisson and continuity equations in a self-consistent way. The main figures of merit are calculated by means of a postprocessing of the output data from device simulation. After the validation of the simulation methodology by means of comparison of the simulation result with literature data, the ultimate efficiency of the IBC-HJ architecture has been calculated. By accounting for all optical losses, IBC-HJ solar cells result in a theoretical maximum efficiency above 23.5% (without texturing at front interface) higher than that of both standard homojunction crystalline silicon (Homogeneous Emitter HE) and front contact heterojuction (Heterojunction with Intrinsic Thin layer HIT) solar cells. However it is clear that the criticalities of this structure are mainly due to the defects density and to the poor carriers transport mobility in the amorphous silicon layers. Lastly, the influence of the most critical geometrical and physical parameters on the main figures of merit have been investigated by applying the numerical simulation tool set-up during the first part of the present thesis. Simulations have highlighted that carrier mobility and defects level in amorphous silicon may lead to a potentially significant reduction of the conversion efficiency.

Ion implantation of organic thin films and electronic devices

Organic semiconductors have great promise in the field of electronics due to their low cost in term of fabrication on large areas and their versatility to new devices, for these reasons they are becoming a great chance in the actual technologic scenery. Some of the most important open issues related to these materials are the effects of surfaces and interfaces between semiconductor and metals, the changes caused by different deposition methods and temperature, the difficulty related to the charge transport modeling and finally a fast aging with time, bias, air and light, that can change the properties very easily. In order to find out some important features of organic semiconductors I fabricated Organic Field Effect Transistors (OFETs), using them as characterization tools. The focus of my research is to investigate the effects of ion implantation on organic semiconductors and on OFETs. Ion implantation is a technique widely used on inorganic semiconductors to modify their electrical properties through the controlled introduction of foreign atomic species in the semiconductor matrix. I pointed my attention on three major novel and interesting effects, that I observed for the first time following ion implantation of OFETs: 1) modification of the electrical conductivity; 2) introduction of stable charged species, electrically active with organic thin films; 3) stabilization of transport parameters (mobility and threshold voltage). I examined 3 different semiconductors: Pentacene, a small molecule constituted by 5 aromatic rings, Pentacene-TIPS, a more complex by-product of the first one, and finally an organic material called Pedot PSS, that belongs to the branch of the conductive polymers. My research started with the analysis of ion implantation of Pentacene films and Pentacene OFETs. Then, I studied totally inkjet printed OFETs made of Pentacene-TIPS or PEDOT-PSS, and the research will continue with the ion implantation on these promising organic devices.

Simulation of Smart Materials

The aim of this thesis is the elucidation of structure-properties relationship of molecular semiconductors for electronic devices. This involves the use of a comprehensive set of simulation techniques, ranging from quantum-mechanical to numerical stochastic methods, and also the development of ad-hoc computational tools. In more detail, the research activity regarded two main topics: the study of electronic properties and structural behaviour of liquid crystalline (LC) materials based on functionalised oligo(p-phenyleneethynylene) (OPE), and the investigation on the electric field effect associated to OFET operation on pentacene thin film stability. In this dissertation, a novel family of substituted OPE liquid crystals with applications in stimuli-responsive materials is presented. In more detail, simulations can not only provide evidence for the characterization of the liquid crystalline phases of different OPEs, but elucidate the role of charge transfer states in donor-acceptor LCs containing an endohedral metallofullerene moiety. Such systems can be regarded as promising candidates for organic photovoltaics. Furthermore, exciton dynamics simulations are performed as a way to obtain additional information about the degree of order in OPE columnar phases. Finally, ab initio and molecular mechanics simulations are used to investigate the influence of an applied electric field on pentacene reactivity and stability. The reaction path of pentacene thermal dimerization in the presence of an external electric field is investigated; the results can be related to the fatigue effect observed in OFETs, that show significant performance degradation even in the absence of external agents. In addition to this, the effect of the gate voltage on a pentacene monolayer are simulated, and the results are then compared to X-ray diffraction measurements performed for the first time on operating OFETs.

Non-staphylococcal infections of cardiac implantable electronic devices

Background. The number of infections of cardiac implantable electronic devices (CIED) continues to escalate out of proportion to the increase rate of device implantation. Staphylococcal organisms account for 70% to 90% of all CIED infections. However, little is known about non-staphylococcal infections, which have been described only in case reports, small case series or combined in larger studies with staphylococcal CIED infections, thereby diluting their individual impact. ^ Methods. A retrospective review of hospital records of patients admitted with a CIED-related infections were identified within four academic hospitals in Houston, Texas between 2002 and 2009. ^ Results. Of the 504 identified patients with CIED-related infection, 80 (16%) had a non-staphylococcal infection and were the focus of this study. Although the demographics and comorbities of subjects were comparable to other reports, our study illustrates many key points: (a) the microbiologic diversity of non-staphylococcal infections was rather extensive, as it included other Gram-positive bacteria like streptococci and enterococci, a variety of Gram-negative bacteria, atypical bacteria including Nocardia and Mycobacteria, and fungi like Candida and Aspergillus; (b) the duration of CIED insertion prior to non-staphylococcal infection was relatively prolong (mean, 109 ± 27 weeks), of these 44% had their device previously manipulated within a mean of 29.5 ± 6 weeks; (c) non-staphylococcal organisms appear to be less virulent, cause prolonged clinical symptoms prior to admission (mean, 48 ± 12.8 days), and are associated with a lower mortality (4%) than staphylococcal organisms; (d) thirteen patients (16%) presented with CIED-related endocarditis; (e) although not described in prior reports, we identified 3 definite and 2 suspected cases of secondary Gram-negative bacteremia seeding of the CIED; and (f) inappropriate antimicrobial coverage was provided in approximately 50% of patients with non-staphylococcal infections for a mean period of 2.1 days. ^ Conclusions. Non-staphylococcal CIED-related infections are prevalent and diverse with a relatively low virulence and mortality rate. Since non-staphylococcal organisms are capable of secondarily seeding the CIED, a high suspicion for CIED-related infection is warranted in patients with bloodstream infection. Additionally, in patients with suspected CIED infection, adequate Gram positive and -negative antibacterial coverage should be administered until microbiologic data become available.^

Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints

La fiabilidad está pasando a ser el principal problema de los circuitos integrados según la tecnología desciende por debajo de los 22nm. Pequeñas imperfecciones en la fabricación de los dispositivos dan lugar ahora a importantes diferencias aleatorias en sus características eléctricas, que han de ser tenidas en cuenta durante la fase de diseño. Los nuevos procesos y materiales requeridos para la fabricación de dispositivos de dimensiones tan reducidas están dando lugar a diferentes efectos que resultan finalmente en un incremento del consumo estático, o una mayor vulnerabilidad frente a radiación. Las memorias SRAM son ya la parte más vulnerable de un sistema electrónico, no solo por representar más de la mitad del área de los SoCs y microprocesadores actuales, sino también porque las variaciones de proceso les afectan de forma crítica, donde el fallo de una única célula afecta a la memoria entera. Esta tesis aborda los diferentes retos que presenta el diseño de memorias SRAM en las tecnologías más pequeñas. En un escenario de aumento de la variabilidad, se consideran problemas como el consumo de energía, el diseño teniendo en cuenta efectos de la tecnología a bajo nivel o el endurecimiento frente a radiación. En primer lugar, dado el aumento de la variabilidad de los dispositivos pertenecientes a los nodos tecnológicos más pequeños, así como a la aparición de nuevas fuentes de variabilidad por la inclusión de nuevos dispositivos y la reducción de sus dimensiones, la precisión del modelado de dicha variabilidad es crucial. Se propone en la tesis extender el método de inyectores, que modela la variabilidad a nivel de circuito, abstrayendo sus causas físicas, añadiendo dos nuevas fuentes para modelar la pendiente sub-umbral y el DIBL, de creciente importancia en la tecnología FinFET. Los dos nuevos inyectores propuestos incrementan la exactitud de figuras de mérito a diferentes niveles de abstracción del diseño electrónico: a nivel de transistor, de puerta y de circuito. El error cuadrático medio al simular métricas de estabilidad y prestaciones de células SRAM se reduce un mínimo de 1,5 veces y hasta un máximo de 7,5 a la vez que la estimación de la probabilidad de fallo se mejora en varios ordenes de magnitud. El diseño para bajo consumo es una de las principales aplicaciones actuales dada la creciente importancia de los dispositivos móviles dependientes de baterías. Es igualmente necesario debido a las importantes densidades de potencia en los sistemas actuales, con el fin de reducir su disipación térmica y sus consecuencias en cuanto al envejecimiento. El método tradicional de reducir la tensión de alimentación para reducir el consumo es problemático en el caso de las memorias SRAM dado el creciente impacto de la variabilidad a bajas tensiones. Se propone el diseño de una célula que usa valores negativos en la bit-line para reducir los fallos de escritura según se reduce la tensión de alimentación principal. A pesar de usar una segunda fuente de alimentación para la tensión negativa en la bit-line, el diseño propuesto consigue reducir el consumo hasta en un 20 % comparado con una célula convencional. Una nueva métrica, el hold trip point se ha propuesto para prevenir nuevos tipos de fallo debidos al uso de tensiones negativas, así como un método alternativo para estimar la velocidad de lectura, reduciendo el número de simulaciones necesarias. Según continúa la reducción del tamaño de los dispositivos electrónicos, se incluyen nuevos mecanismos que permiten facilitar el proceso de fabricación, o alcanzar las prestaciones requeridas para cada nueva generación tecnológica. Se puede citar como ejemplo el estrés compresivo o extensivo aplicado a los fins en tecnologías FinFET, que altera la movilidad de los transistores fabricados a partir de dichos fins. Los efectos de estos mecanismos dependen mucho del layout, la posición de unos transistores afecta a los transistores colindantes y pudiendo ser el efecto diferente en diferentes tipos de transistores. Se propone el uso de una célula SRAM complementaria que utiliza dispositivos pMOS en los transistores de paso, así reduciendo la longitud de los fins de los transistores nMOS y alargando los de los pMOS, extendiéndolos a las células vecinas y hasta los límites de la matriz de células. Considerando los efectos del STI y estresores de SiGe, el diseño propuesto mejora los dos tipos de transistores, mejorando las prestaciones de la célula SRAM complementaria en más de un 10% para una misma probabilidad de fallo y un mismo consumo estático, sin que se requiera aumentar el área. Finalmente, la radiación ha sido un problema recurrente en la electrónica para aplicaciones espaciales, pero la reducción de las corrientes y tensiones de los dispositivos actuales los está volviendo vulnerables al ruido generado por radiación, incluso a nivel de suelo. Pese a que tecnologías como SOI o FinFET reducen la cantidad de energía colectada por el circuito durante el impacto de una partícula, las importantes variaciones de proceso en los nodos más pequeños va a afectar su inmunidad frente a la radiación. Se demuestra que los errores inducidos por radiación pueden aumentar hasta en un 40 % en el nodo de 7nm cuando se consideran las variaciones de proceso, comparado con el caso nominal. Este incremento es de una magnitud mayor que la mejora obtenida mediante el diseño de células de memoria específicamente endurecidas frente a radiación, sugiriendo que la reducción de la variabilidad representaría una mayor mejora. ABSTRACT Reliability is becoming the main concern on integrated circuit as the technology goes beyond 22nm. Small imperfections in the device manufacturing result now in important random differences of the devices at electrical level which must be dealt with during the design. New processes and materials, required to allow the fabrication of the extremely short devices, are making new effects appear resulting ultimately on increased static power consumption, or higher vulnerability to radiation SRAMs have become the most vulnerable part of electronic systems, not only they account for more than half of the chip area of nowadays SoCs and microprocessors, but they are critical as soon as different variation sources are regarded, with failures in a single cell making the whole memory fail. This thesis addresses the different challenges that SRAM design has in the smallest technologies. In a common scenario of increasing variability, issues like energy consumption, design aware of the technology and radiation hardening are considered. First, given the increasing magnitude of device variability in the smallest nodes, as well as new sources of variability appearing as a consequence of new devices and shortened lengths, an accurate modeling of the variability is crucial. We propose to extend the injectors method that models variability at circuit level, abstracting its physical sources, to better model sub-threshold slope and drain induced barrier lowering that are gaining importance in FinFET technology. The two new proposed injectors bring an increased accuracy of figures of merit at different abstraction levels of electronic design, at transistor, gate and circuit levels. The mean square error estimating performance and stability metrics of SRAM cells is reduced by at least 1.5 and up to 7.5 while the yield estimation is improved by orders of magnitude. Low power design is a major constraint given the high-growing market of mobile devices that run on battery. It is also relevant because of the increased power densities of nowadays systems, in order to reduce the thermal dissipation and its impact on aging. The traditional approach of reducing the voltage to lower the energy consumption if challenging in the case of SRAMs given the increased impact of process variations at low voltage supplies. We propose a cell design that makes use of negative bit-line write-assist to overcome write failures as the main supply voltage is lowered. Despite using a second power source for the negative bit-line, the design achieves an energy reduction up to 20% compared to a conventional cell. A new metric, the hold trip point has been introduced to deal with new sources of failures to cells using a negative bit-line voltage, as well as an alternative method to estimate cell speed, requiring less simulations. With the continuous reduction of device sizes, new mechanisms need to be included to ease the fabrication process and to meet the performance targets of the successive nodes. As example we can consider the compressive or tensile strains included in FinFET technology, that alter the mobility of the transistors made out of the concerned fins. The effects of these mechanisms are very dependent on the layout, with transistor being affected by their neighbors, and different types of transistors being affected in a different way. We propose to use complementary SRAM cells with pMOS pass-gates in order to reduce the fin length of nMOS devices and achieve long uncut fins for the pMOS devices when the cell is included in its corresponding array. Once Shallow Trench isolation and SiGe stressors are considered the proposed design improves both kinds of transistor, boosting the performance of complementary SRAM cells by more than 10% for a same failure probability and static power consumption, with no area overhead. While radiation has been a traditional concern in space electronics, the small currents and voltages used in the latest nodes are making them more vulnerable to radiation-induced transient noise, even at ground level. Even if SOI or FinFET technologies reduce the amount of energy transferred from the striking particle to the circuit, the important process variation that the smallest nodes will present will affect their radiation hardening capabilities. We demonstrate that process variations can increase the radiation-induced error rate by up to 40% in the 7nm node compared to the nominal case. This increase is higher than the improvement achieved by radiation-hardened cells suggesting that the reduction of process variations would bring a higher improvement.

Simulation of the secondary electrons energy deposition produced by proton beams in PMMA: influence of the target electronic excitation description

We have studied the radial dependence of the energy deposition of the secondary electron generated by swift proton beams incident with energies T = 50 keV–5 MeV on poly(methylmethacrylate) (PMMA). Two different approaches have been used to model the electronic excitation spectrum of PMMA through its energy loss function (ELF), namely the extended-Drude ELF and the Mermin ELF. The singly differential cross section and the total cross section for ionization, as well as the average energy of the generated secondary electrons, show sizeable differences at T ⩽ 0.1 MeV when evaluated with these two ELF models. In order to know the radial distribution around the proton track of the energy deposited by the cascade of secondary electrons, a simulation has been performed that follows the motion of the electrons through the target taking into account both the inelastic interactions (via electronic ionizations and excitations as well as electron-phonon and electron trapping by polaron creation) and the elastic interactions. The radial distribution of the energy deposited by the secondary electrons around the proton track shows notable differences between the simulations performed with the extended-Drude ELF or the Mermin ELF, being the former more spread out (and, therefore, less peaked) than the latter. The highest intensity and sharpness of the deposited energy distributions takes place for proton beams incident with T ~ 0.1–1 MeV. We have also studied the influence in the radial distribution of deposited energy of using a full energy distribution of secondary electrons generated by proton impact or using a single value (namely, the average value of the distribution); our results show that differences between both simulations become important for proton energies larger than ~0.1 MeV. The results presented in this work have potential applications in materials science, as well as hadron therapy (due to the use of PMMA as a tissue phantom) in order to properly consider the generation of electrons by proton beams and their subsequent transport and energy deposition through the target in nanometric scales.

Measuring geometric phases of scattering states in nanoscale electronic devices

We show how a quantum property, a geometric phase, associated with scattering states can be exhibited in nanoscale electronic devices. We propose an experiment to use interference to directly measure the effect of this geometric phase. The setup involves a double-path interferometer, adapted from that used to measure the phase evolution of electrons as they traverse a quantum dot (QD). Gate voltages on the QD could be varied cyclically and adiabatically, in a manner similar to that used to observe quantum adiabatic charge pumping. The interference due to the geometric phase results in oscillations in the current collected in the drain when a small bias across the device is applied. We illustrate the effect with examples of geometric phases resulting from both Abelian and non-Abelian gauge potentials.

Logical simulation of communication subsystem for Universal Serial Bus (USB)

The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them. In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.

Modeling and simulation of bulk gallium nitride power semiconductor devices

Bulk gallium nitride (GaN) power semiconductor devices are gaining significant interest in recent years, creating the need for technology computer aided design (TCAD) simulation to accurately model and optimize these devices. This paper comprehensively reviews and compares different GaN physical models and model parameters in the literature, and discusses the appropriate selection of these models and parameters for TCAD simulation. 2-D drift-diffusion semi-classical simulation is carried out for 2.6 kV and 3.7 kV bulk GaN vertical PN diodes. The simulated forward current-voltage and reverse breakdown characteristics are in good agreement with the measurement data even over a wide temperature range.

Acoustic Simulation of a Special Switched Reluctance Drive by Means of Field-Circuit Coupling and Multiphysics Simulation

The approach presented in this paper consists of an energy-based field-circuit coupling in combination with multi-physics simulation of the acoustic radiation of electrical machines. The proposed method is applied to a special switched reluctance motor with asymmetric pole geometry to improve the start-up torque. The pole shape has been optimized, subject to low torque ripple, in a previous study. The proposed approach here is used to analyze the impact of the optimization on the overall acoustic behavior. The field-circuit coupling is based on a temporary lumped-parameter model of the magnetic part incorporated into a circuit simulation based on the modified nodal analysis. The harmonic force excitation is calculated by means of stress tensor computation, and it is transformed to a mechanical mesh by mapping techniques. The structural dynamic problem is solved in the frequency domain using a finite-element modal analysis and superposition. The radiation characteristic is obtained from boundary element acoustic simulation. Simulation results of both rotor types are compared, and measurements of the drive are presented.