Describing syntax with star-free regular expressions

Koskenniemen Äärellistilaisen leikkauskieliopin (FSIG) lauseopilliset rajoitteet ovat loogisesti vähemmän kompleksisia kuin mihin niissä käytetty formalismi vittaisi. Osoittautuukin että vaikka Voutilaisen (1994) englannin kielelle laatima FSIG-kuvaus käyttää useita säännöllisten lausekkeiden laajennuksia, kieliopin kuvaus kokonaisuutenaan palautuu äärelliseen yhdistelmään unionia, komplementtia ja peräkkäinasettelua. Tämä on oleellinen parannus ENGFSIG:n descriptiiviseen kompleksisuuteen. Tulos avaa ovia FSIG-kuvauksen loogisten ominaisuuksien syvemmälle analyysille ja FSIG kuvausten mahdolliselle optimoinnillle. Todistus sisältää uuden kaavan, joka kääntää Koskenniemien rajoiteoperaation ilman markkerimerkkejä.

Regular versus alternating (FeS4)(n) chains: Magnetism in KFeS2 and CsFeS2

We report crystal magnetic susceptibility results of two S = 1/2 one-dimensional Heisenberg antiferromagnets, KFeS2 and CsFeS2. Both compounds consist of (FeS4)(n) chains with an average Fe-Fe distance of 2.7 Angstrom. In KFeS2, all intrachain Fe-Fe distances are identical. Its magnetic susceptibility is typical of a regular antiferromagnetic chain with spin-spin exchange parameter J = -440.7 K. In CsFeS2, however, the Fe-Fe distances alternate between 2.61 and 2.82 Angstrom. This is reflected in its magnetic susceptibility, which could be fitted with J = -640 K, and the degree of alternation, alpha = 0.3. These compounds form a unique pair, and allow for a convenient experimental comparison of the magnetic properties of regular versus alternating Heisenberg chains.

Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks

Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dataflow graphs have been widely regarded as a powerful programming model for DSP applications. In this paper we propose a method to minimize buffer storage requirement in constructing rate-optimal compile-time (MBRO) schedules for multi-rate dataflow graphs. We demonstrate that the constraints to minimize buffer storage while executing at the optimal computation rate (i.e. the maximum possible computation rate without storage constraints) can be formulated as a unified linear programming problem in our framework. A novel feature of our method is that in constructing the rate-optimal schedule, it directly minimizes the memory requirement by choosing the schedule time of nodes appropriately. Lastly, a new circular-arc interval graph coloring algorithm has been proposed to further reduce the memory requirement by allowing buffer sharing among the arcs of the multi-rate dataflow graph. We have constructed an experimental testbed which implements our MBRO scheduling algorithm as well as (i) the widely used periodic admissible parallel schedules (also known as block schedules) proposed by Lee and Messerschmitt (IEEE Transactions on Computers, vol. 36, no. 1, 1987, pp. 24-35), (ii) the optimal scheduling buffer allocation (OSBA) algorithm of Ning and Gao (Conference Record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Charleston, SC, Jan. 10-13, 1993, pp. 29-42), and (iii) the multi-rate software pipelining (MRSP) algorithm (Govindarajan and Gao, in Proceedings of the 1993 International Conference on Application Specific Array Processors, Venice, Italy, Oct. 25-27, 1993, pp. 77-88). Schedules generated for a number of random dataflow graphs and for a set of DSP application programs using the different scheduling methods are compared. The experimental results have demonstrated a significant improvement (10-20%) in buffer requirements for the MBRO schedules compared to the schedules generated by the other three methods, without sacrificing the computation rate. The MBRO method also gives a 20% average improvement in computation rate compared to Lee's Block scheduling method.

On limiting cases in the flexure of simply supported regular polygonal plates

Limiting solutions are derived for the flexure of simply supported many-sided regular polygons, as the number of sides is increased indefinitely. It is shown that these solutions are different from those for simply supported circular plates. For axisymmetric loading, circular plate solutions overestimate the deflexions and the moments by significant factors.

Dynamically Reconfigurable Regular Expression Matching Architecture

Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Nondeterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further,we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.

A Combinatorial Family of Near Regular LDPC Codes

An elementary combinatorial Tanner graph construction for a family of near-regular low density parity check (LDPC) codes achieving high girth is presented. These codes are near regular in the sense that the degree of a left/right vertex is allowed to differ by at most one from the average. The construction yields in quadratic time complexity an asymptotic code family with provable lower bounds on the rate and the girth for a given choice of block length and average degree. The construction gives flexibility in the choice of design parameters of the code like rate, girth and average degree. Performance simulations of iterative decoding algorithm for the AWGN channel on codes designed using the method demonstrate that these codes perform better than regular PEG codes and MacKay codes of similar length for all values of Signal to noise ratio.

Role of Nonplanar Peptide Unit in Regular Polypeptide Helices - New Model for Pply-Beta-Benzyl-L-Aspartate

The effect of non-planarity of the peptide unit on helical structures stabilized by intrachain hydrogen bonds is discussed. While the present calculations generally agree with those already reported in the literature for right-handed helical structures, it is found that the most stable left-handed structure is a novel helix, called the delta-helix. Its helical parameters are close to these reported for poly-beta-benzyl-L -aspartate. Conformational energy calculations show that poly-beta-benzyl-L -aspartate with the delta-helical structure is considerably more stable than the structure it is generally believed to take up (the omega-helix) by about 15 kcal/mol-residue.

Efficient Regular Expression Pattern Matching for Network Intrusion Detection Systems using Modified Word-based Automata

Network Intrusion Detection Systems (NIDS) intercept the traffic at an organization's network periphery to thwart intrusion attempts. Signature-based NIDS compares the intercepted packets against its database of known vulnerabilities and malware signatures to detect such cyber attacks. These signatures are represented using Regular Expressions (REs) and strings. Regular Expressions, because of their higher expressive power, are preferred over simple strings to write these signatures. We present Cascaded Automata Architecture to perform memory efficient Regular Expression pattern matching using existing string matching solutions. The proposed architecture performs two stage Regular Expression pattern matching. We replace the substring and character class components of the Regular Expression with new symbols. We address the challenges involved in this approach. We augment the Word-based Automata, obtained from the re-written Regular Expressions, with counter-based states and length bound transitions to perform Regular Expression pattern matching. We evaluated our architecture on Regular Expressions taken from Snort rulesets. We were able to reduce the number of automata states between 50% to 85%. Additionally, we could reduce the number of transitions by a factor of 3 leading to further reduction in the memory requirements.

Performance improvement of short-length regular low-density parity-check codes with low-complexity post-processing

It is well known that extremely long low-density parity-check (LDPC) codes perform exceptionally well for error correction applications, short-length codes are preferable in practical applications. However, short-length LDPC codes suffer from performance degradation owing to graph-based impairments such as short cycles, trapping sets and stopping sets and so on in the bipartite graph of the LDPC matrix. In particular, performance degradation at moderate to high E-b/N-0 is caused by the oscillations in bit node a posteriori probabilities induced by short cycles and trapping sets in bipartite graphs. In this study, a computationally efficient algorithm is proposed to improve the performance of short-length LDPC codes at moderate to high E-b/N-0. This algorithm makes use of the information generated by the belief propagation (BP) algorithm in previous iterations before a decoding failure occurs. Using this information, a reliability-based estimation is performed on each bit node to supplement the BP algorithm. The proposed algorithm gives an appreciable coding gain as compared with BP decoding for LDPC codes of a code rate equal to or less than 1/2 rate coding. The coding gains are modest to significant in the case of optimised (for bipartite graph conditioning) regular LDPC codes, whereas the coding gains are huge in the case of unoptimised codes. Hence, this algorithm is useful for relaxing some stringent constraints on the graphical structure of the LDPC code and for developing hardware-friendly designs.

Analysis of the degrees-of-freedom of spatial parallel manipulators in regular and singular configurations

This paper presents a study of the nature of the degrees-of-freedom of spatial manipulators based on the concept of partition of degrees-of-freedom. In particular, the partitioning of degrees-of-freedom is studied in five lower-mobility spatial parallel manipulators possessing different combinations of degrees-of-freedom. An extension of the existing theory is introduced so as to analyse the nature of the gained degree(s)-of-freedom at a gain-type singularity. The gain of one- and two-degrees-of-freedom is analysed in several well-studied, as well as newly developed manipulators. The formulations also present a basis for the analysis of the velocity kinematics of manipulators of any architecture. (C) 2013 Elsevier Ltd. All rights reserved.

Diagnóstico de las empresas familiares con estudiantes de Lic. En Agronegocios, modalidad regular, Facultad de Desarrollo Rural, Universidad Nacional Agraria, año 2014

La empresa familiar forma parte fundamental de las estructuras productivas, tanto de las economías industrializadas como en vías de desarrollo; a pesar de carecer de datos rigorosos que permitan corroborarlo, la empresa familiar tiene un papel preponderante en la generación de riqueza nacional; el objetivo fundamental del estudio fue conocer el grado de conocimiento y el rol que ejercen los estudiantes en una empresa familiar y el número de empresas familiares existentes en la carrera de Lic. Agronegocios, Facultad de Desarrollo Rural, Universidad Nacional Agraria- Managua, esto se realizó a través de la implementación de encuesta a los estudiantes que formaron parte de la muestra logrando realizar posteriormente un análisis de datos que facilitó la redacción del documento presentado a continuación; la ejecución de esta temática se dio debido la poca importancia que se le ha dado al tema de las empresas familiares dentro de la economía de Nicaragua a pesar de que estas aportan el 50% del PIB, la falta de información y estudios relacionados que nos ayuden a conocer la realidad de estas empresas tanto en el ámbito organizativo como en el económico; de las negocios encontrados entre la muestra el 33% forma parte de las MIPYMES divididos el 21% en la micro empresas, el 8% en la pequeña empresa y el 3% en la mediana empresa, el 67% restante de la muestra total son negocios de emprendimiento categorizados así por facturar menos de 37360.83 dólares; por otro parte el 18% de los estudiantes matriculados en la Lic. Agronegocios forman parte de una empresa familiar de este porcentaje el 10% tiene conocimiento amplio sobre la temática, un 14 % posee únicamente ciertos conocimientos derivados de algunos temas relacionados mientras que el 76% no tienen ningún tipo de conocimiento acerca de la temática.