Future switching technology: bacterial protein-based programmable all-optical switch for integrated optics applications?

We report on the bacterial protein-based all-optical switches which operate at low laser power, high speed and fulfil most of the requirements to be an ideal all-optical switch without any moving parts involved. This consists of conventional optical waveguides coated with bacteriorhodopsin films at switching locations. The principle of operation of the switch is based on the light-induced refractive index change of bacteriorhodopsin. This approach opens the possibility of realizing proteinbased all-optical switches for communication network, integrated optics and optical computers.

A microprocessor-controlled programmable pulse generator

The hardware and the software details of a user-friendly, simple, flexible and inexpensive pulse programmer using programmable counters interfaced to a microprocessor are described. The control of the various parameters that are required for NMR applications is implemented using the microprocessor. The basic hardware is extendable to other applications which require programmable pulse trains.

Foldable compatibility matrix for the folding of programmable logic arrays

This paper describes a switching theoretic algorithm for the folding of programmable logic arrays (PLA). The algorithm is valid for both column and row folding, although it has been presented considering only the simple column folding. The pairwise compatibility relations among all the pairs of the columns of the PLA are mapped into a square matrix, called the compatibility matrix of the PLA. A foldable compatibility matrix (FCM), a new concept introduced by the author, is then derived from the compatibility matrix. A new theorem called the folding theorem is then proved. The theorem states that the existence of an m by 2m FCM is both necessary and sufficient to fold 2m columns of the n column PLA (2m ≤ n). Once an FCM is obtained, the ordered pairs of foldable columns and the re-ordering of the rows are readily determined.

'A programmable digital signal averager' Reply

In a recent paper, Srinivasan et al (1980) have described a programmable digital signal averager with facility for programming the sampling period, number of channels and number of sweeps. We have examined this paper in some detail and find that some points need clarification.

A Simple Programmable 2-Pulse Generator for Pulsed NMR NQR Applications

Programmable pulse generator (PPG) circuits using programmable interval timer chips are normally based on a PC or a microprocessor. We describe here a simple low cost programmable two-pulse generator using Intel 8253s in a stand-alone mode, eliminating the need for a PC or a microprocessor, though our design also can be operated via a PC or a microprocessor.

Exploiting Programmable Network Interfaces for Parallel Query Execution in Workstation Clusters

Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel application run on them. In this paper, we propose schemes where certain application level processing in parallel database query execution is performed on the network processor. We evaluate the performance of TPC-H queries executing on a high end cluster where all tuple processing is done on the host processor, using a timed Petri net model, and find that tuple processing costs on the host processor dominate the execution time. These results are validated using a small cluster. We therefore propose 4 schemes where certain tuple processing activity is offloaded to the network processor. The first 2 schemes offload the tuple splitting activity - computation to identify the node on which to process the tuples, resulting in an execution time speedup of 1.09 relative to the base scheme, but with I/O bus becoming the bottleneck resource. In the 3rd scheme in addition to offloading tuple processing activity, the disk and network interface are combined to avoid the I/O bus bottleneck, which results in speedups up to 1.16, but with high host processor utilization. Our 4th scheme where the network processor also performs apart of join operation along with the host processor, gives a speedup of 1.47 along with balanced system resource utilizations. Further we observe that the proposed schemes perform equally well even in a scaled architecture i.e., when the number of processors is increased from 2 to 64

On a programmable signal processor for VLSI

This paper presents a method of designing a programmable signal processor based on a bit parallel matrix vector matrix multiplier (linear transformer). The salient feature of this design is that the efficiency of the direct vector matrix multiplier is improved and VLSI design is made much simpler by trading off the more expensive arithematic operation (multiplication) for 'cheaper' manipulation (addition/subtraction) of the data.

Evaluating shock absorption behavior of small-sized systems under programmable electric field

A simple ball-drop impact tester is developed for studying the dynamic response of hierarchical, complex, small-sized systems and materials. The developed algorithm and set-up have provisions for applying programmable potential difference along the height of a test specimen during an impact loading; this enables us to conduct experiments on various materials and smart structures whose mechanical behavior is sensitive to electric field. The software-hardware system allows not only acquisition of dynamic force-time data at very fast sampling rate (up to 2 x 10(6) samples/s), but also application of a pre-set potential difference (up to +/- 10 V) across a test specimen for a duration determined by feedback from the force-time data. We illustrate the functioning of the set-up by studying the effect of electric field on the energy absorption capability of carbon nanotube foams of 5 x 5 x 1.2 mm(3) size under impact conditions. (C) 2014 AIP Publishing LLC.

Pulse compression by filamentation in argon with an acoustic optical programmable dispersive filter for predispersion compensation

We have experimentally demonstrated pulses 0.4 mJ in duration smaller than 12 fs; with an excellent spatial beam profile by self-guided propagation in argon. The original 52 fs pulses from the chirped pulsed amplification laser system are first precompressed to 32 fs by inserting an acoustic optical programmable dispersive filter instrument into the laser system for spectrum reshaping and dispersion compensation, and the pulse spectrum is subsequently broadened by filamentation in an argon cell. By using chirped mirrors for post-dispersion compensation, the pulses are successfully compressed to smaller than 12 fs.

Nonautonomous elementary net systems and their application to programmable logic control

In this paper, a novel approach to Petri net modeling of programmable logic controller (PLC) programs is presented. The modeling approach is a simple extension of elementary net systems, and a graphical design tool that supports the use of this modeling approach is provided. A key characteristic of the model is that the binary sensory inputs and binary actuation outputs of the PLC are explicitly represented. This leads to the following two improvements: outputs are unambiguous, and interaction patterns are more clearly represented in the graphical form. The use of this modeling approach produces programs that are simple, lightweight, and portable. The approach is demonstrated by applying it to the development of a control module for a MonTech Positioning Station. © 2008 IEEE.

Voltage programmable dual-band bandpass/bandstop filter response in a single micro-electro-mechanical device

This paper reports on a switchable multi-band filter response achieved within a single micro-electro-mechanical device. A prototype device fabricated in a SOI process demonstrates a voltage programmable and tunable, dual-band, band-pass/band-stop response. Both analytical and finite element models are introduced in this paper to elucidate the operating principle of the filter and to guide filter design. Voltage programmability of the filter characteristic is demonstrated with the ability to independently tune the centre frequency and bandwidth for each band. A representative measurement shows that the minimum 3 dB-bandwidth (BW) is 155 Hz, 140Hz, and 20 dB-BW is 216 Hz, 203Hz for the upper-band and lower-band center frequencies located at 131.5 kHz and 130.7 kHz, respectively. © 2011 IEEE.

Programmable ZnO nanowire transistors using switchable polarization of ferroelectric liquid crystal

We demonstrate modulations of electrical conductance and hysteresis behavior in ZnO nanowire transistors via electrically polarized switching of ferroelectric liquid crystal (FLC). After coating a nanowire channel in the transistors with FLCs, we observed large increases in channel conductance and hysteresis width, and a strong dependence of hysteresis loops on the polarization states associated with the orientation of electric dipole moments along the direction of the gate electric field. Furthermore, the reversible switching and retention characteristics provide the feasibility of creating a hybrid system with switch and memory functions. © 2013 American Institute of Physics.