Reduction of Torque Ripple in Induction Motor Drives Using an AdvancedHybrid PWM Technique

A voltage source inverter-fed induction motor produces a pulsating torque due to application of nonsinusoidal voltages. Torque pulsation is strongly influenced by the pulsewidth modulation (PWM) method employed. Conventional space vector PWM (CSVPWM) is known to result in less torque ripple than sine-triangle PWM. This paper aims at further reduction in the pulsating torque by employing advanced bus-clamping switching sequences, which apply an active vector twice in a subcycle. This paper proposes a hybrid PWM technique which employs such advanced bus-clamping sequences in conjunction with a conventional switching sequence. The proposed hybrid PWM technique is shown to reduce the torque ripple considerably over CSVPWM along with a marginal reduction in current ripple.

Switching frequency variation control in hysteresis PWM controller for IM drives using variable parabolic bands for current error space phasor

Variation of switching frequency over the entire operating speed range of an induction motor (M drive is the major problem associated with conventional two-level three-phase hysteresis controller as well as the space phasor based PWM hysteresis controller. This paper describes a simple hysteresis current controller for controlling the switching frequency variation in the two-level PWM inverter fed IM drives for various operating speeds. A novel concept of continuously variable hysteresis boundary of current error space phasor with the varying speed of the IM drive is proposed in the present work. The variable parabolic boundary for the current error space phasor is suggested for the first time in this paper for getting the switching frequency pattern with the hysteresis controller, similar to that of the constant switching frequency voltage-controlled space vector PWM (VC-SVPWM) based inverter fed IM drive. A generalized algorithm is also developed to determine parabolic boundary for controlling the switching frequency variation, for any IM load. Only the adjacent inverter voltage vectors forming a triangular sector, in which tip of the machine voltage vector ties, are switched to keep current error space vector within the parabolic boundary. The controller uses a self-adaptive sector identification logic, which provides smooth transition between the sectors and is capable of taldng the inverter up to six-step mode of operation, if demanded by drive system. The proposed scheme is simulated and experimentally verified on a 3.7 kW IM drive.

Generation of parabolic trajectories for current error space phasor similar to an SVPWM controller for control of switching frequency variation in current hysteresis PWM controlled IM drives

Switching frequency variation over a fundamental period is a major problem associated with hysteresis controller based VSI fed IM drives. This paper describes a novel concept of generating parabolic trajectories for current error space phasor for controlling the switching frequency variation in the hysteresis controller based two-level inverter fed IM drives. A generalized algorithm is developed to determine unique set of parabolic trajectories for different speeds of operation for any given IM load. Proposed hysteresis controller provides the switching frequency spectrum of inverter output voltage, similar to that of the constant switching frequency VC-SVPWM based IM drive. The scheme is extensively simulated and experimentally verified on a 3.7 kW IM drive for steady state and transient performance.

A Computationally Efficient PWM Algorithm for Multilevel Inverters

Centred space vector PWM (CSVPWM) technique is popularly used for three level voltage source inverters. The reference voltage vector is synthesized by time-averaging of the three nearest voltage vectors produced by the inverter. Identifying the three voltage vectors, and calculation of the dwelling time for each vector are both computationally intensive. This paper analyses the process of PWM generation in CSVPWM. This analysis breaks up a three-level inverter into six different conceptual two level inverters in different regions of the fundamental cycle. Control of 3-level inverter is viewed as the control of the appropriate 2-level inverter. The analysis leads to a systematic simplification of the computations involved, finally resulting in a computationally efficient PWM algorithm. This algorithm exploits the equivalence between triangle comparison and space vector approaches to PWM generation. This algorithm does not involve any 3-phase/2-phase or 2-phase/3-phase transformation. This also does not involve any transformation from rectangular to polar coordinates, and vice versa. Further no evaluation of trigonometric functions is necessary. This algorithm also provides for the mitigation of DC neutral point unbalance, and is well suited to digital implementation. Simulation and experimental results are presented.

A Resonant Integrator Based PLL and AC Current Controller for Single Phase Grid Connected PWM-VSI

Grid connected PWM-VSIs are being increasingly used for applications such as Distributed Generation (DG), power quality, UPS etc. Appropriate control strategies for grid synchronisation and line current regulation are required to establish such a grid interconnection and power transfer. Control of three phase VSIs is widely reported in iterature. Conventionally, dq control in Synchronous Reference Frame(SRF) is employed for both PLL and line current control where PI-controllers are used to track the DC references. Single phase systems do not have defined direct (d) and quadrature (q) axis components that are required for SRF transformation. Thus, references are AC in nature and hence usage of PI controllers cannot yield zero steady state errors. Resonant controllers have the ability to track AC references accurately. In this work, a resonant controller based single phase PLL and current control technique are being employed for tracking grid frequency and the AC current reference respectively. A single phase full bridge converter is being operated as a STATCOM for performance evaluation of the control scheme.

Adaptive Harmonic Elimination Technique in Single Phase PWM Inverters

High frequency PWM inverters produce an output voltage spectrum at the fundamental reference frequency and around the switching frequency. Thus ideally PWM inverters do not introduce any significant lower order harmonics. However, in real systems, due to dead-time effect, device drops and other non-idealities lower order harmonics are present. In order to attenuate these lower order harmonics and hence to improve the quality of output current, this paper presents an \emph{adaptive harmonic elimination technique}. This technique uses an adaptive filter to estimate a particular harmonic that is to be attenuated and generates a voltage reference which will be added to the voltage reference produced by the current control loop of the inverter. This would have an effect of cancelling the voltage that was producing the particular harmonic. The effectiveness and the limitations of the technique are verified experimentally in a single phase PWM inverter in stand-alone as well as g rid interactive modes of operation.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.

Simplified implementation of space vector PWM strategies for a three level inverter

Space vector based PWM strategies for three-level inverters have a broader choice of switching sequences to generate the required reference vector than triangle comparison based PWM techniques. However, space vector based PWM involves numerous steps which are computationally intensive. A simplified algorithm is proposed here, which is shown to reduce the computation time significantly. The developed algorithm is used to implement synchronous and asynchronous conventional space vector PWM, synchronized modified space vector PWM and an asynchronous advanced bus-clamping PWM technique on a low-cost dsPIC digital controller. Experimental results are presented for a comparative evaluation of the performance of different PWM methods.

Circulating power test setup for a PWM rectifier motor drive

Power converters burn-in test consumes large amount of energy, which increases the cost of testing, and certification, in medium and high power application. A simple test configuration to test a PWM rectifier induction motor drive, using a Doubly Fed Induction Machine (DFIM) to circulate power back to the grid for burn-in test is presented. The test configuration makes use of only one power electronic converter, which is the converter to be tested. The test method ensures soft synchronization of DFIM and Squirrel Cage Induction Machine (SCIM). A simple volt per hertz control of the drive is sufficient for conducting the test. To synchronize the DFIM with SCIM, the rotor terminal voltage of DFIM is measured and used as an indication of speed mismatch between DFIM and SCIM. The synchronization is done when the DFIM rotor voltage is at its minimum. Analysis of the DFIM characteristics confirms that such a test can be effectively performed with smooth start up and loading of the test setup. After synchronization is obtained, the speed command to SCIM is changed in order to load the setup in motoring or regenerative mode of operation. The experimental results are presented that validates the proposed test method.

Common-mode filter design for PWM rectifier-based motor drives

A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter.

Space vector-based analysis of overmodulation in triangle-comparison based PWM for voltage source inverter

The equivalence of triangle-comparison-based pulse width modulation (TCPWM) and space vector based PWM (SVPWM) during linear modulation is well-known. This paper analyses triangle-comparison based PWM techniques (TCPWM) such as sine-triangle PWM (SPWM) and common-mode voltage injection PWM during overmodulation from a space vector point of view. The average voltage vector produced by TCPWM during overmodulation is studied in the stationary (a-b) reference frame. This is compared and contrasted with the average voltage vector corresponding to the well-known standard two-zone algorithm for space vector modulated inverters. It is shown that the two-zone overmodulation algorithm itself can be derived from the variation of average voltage vector with TCPWM. The average voltage vector is further studied in a synchronously revolving (d-q) reference frame. The RMS value of low-order voltage ripple can be estimated, and can be used to compare harmonic distortion due to different PWM methods during overmodulation. The measured values of the total harmonic distortion (THD) in the line currents are presented at various fundamental frequencies. The relative values of measured current THD pertaining to different PWM methods tally with those of analytically evaluated RMS voltage ripple.

Apparatus and method for heat-run test on high-power PWM converters with low energy expenditure

Before installation, a voltage source converter is usually subjected to heat-run test to verify its thermal design and performance under load. For heat-run test, the converter needs to be operated at rated voltage and rated current for a substantial length of time. Hence, such tests consume huge amount of energy in case of high-power converters. Also, the capacities of the source and loads available in the research and development (R&D) centre or the production facility could be inadequate to conduct such tests. This paper proposes a method to conduct heat-run tests on high-power, pulse width modulated (PWM) converters with low energy consumption. The experimental set-up consists of the converter under test and another converter (of similar or higher rating), both connected in parallel on the ac side and open on the dc side. Vector-control or synchronous reference frame control is employed to control the converters such that one draws certain amount of reactive power and the other supplies the same; only the system losses are drawn from the mains. The performance of the controller is validated through simulation and experiments. Experimental results, pertaining to heat-run tests on a high-power PWM converter, are presented at power levels of 25 kVA to 150 kVA.