Approche efficace pour la conception des architectures multiprocesseurs sur puce électronique

Les systèmes multiprocesseurs sur puce électronique (On-Chip Multiprocessor [OCM]) sont considérés comme les meilleures structures pour occuper l'espace disponible sur les circuits intégrés actuels. Dans nos travaux, nous nous intéressons à un modèle architectural, appelé architecture isométrique de systèmes multiprocesseurs sur puce, qui permet d'évaluer, de prédire et d'optimiser les systèmes OCM en misant sur une organisation efficace des nœuds (processeurs et mémoires), et à des méthodologies qui permettent d'utiliser efficacement ces architectures. Dans la première partie de la thèse, nous nous intéressons à la topologie du modèle et nous proposons une architecture qui permet d'utiliser efficacement et massivement les mémoires sur la puce. Les processeurs et les mémoires sont organisés selon une approche isométrique qui consiste à rapprocher les données des processus plutôt que d'optimiser les transferts entre les processeurs et les mémoires disposés de manière conventionnelle. L'architecture est un modèle maillé en trois dimensions. La disposition des unités sur ce modèle est inspirée de la structure cristalline du chlorure de sodium (NaCl), où chaque processeur peut accéder à six mémoires à la fois et où chaque mémoire peut communiquer avec autant de processeurs à la fois. Dans la deuxième partie de notre travail, nous nous intéressons à une méthodologie de décomposition où le nombre de nœuds du modèle est idéal et peut être déterminé à partir d'une spécification matricielle de l'application qui est traitée par le modèle proposé. Sachant que la performance d'un modèle dépend de la quantité de flot de données échangées entre ses unités, en l'occurrence leur nombre, et notre but étant de garantir une bonne performance de calcul en fonction de l'application traitée, nous proposons de trouver le nombre idéal de processeurs et de mémoires du système à construire. Aussi, considérons-nous la décomposition de la spécification du modèle à construire ou de l'application à traiter en fonction de l'équilibre de charge des unités. Nous proposons ainsi une approche de décomposition sur trois points : la transformation de la spécification ou de l'application en une matrice d'incidence dont les éléments sont les flots de données entre les processus et les données, une nouvelle méthodologie basée sur le problème de la formation des cellules (Cell Formation Problem [CFP]), et un équilibre de charge de processus dans les processeurs et de données dans les mémoires. Dans la troisième partie, toujours dans le souci de concevoir un système efficace et performant, nous nous intéressons à l'affectation des processeurs et des mémoires par une méthodologie en deux étapes. Dans un premier temps, nous affectons des unités aux nœuds du système, considéré ici comme un graphe non orienté, et dans un deuxième temps, nous affectons des valeurs aux arcs de ce graphe. Pour l'affectation, nous proposons une modélisation des applications décomposées en utilisant une approche matricielle et l'utilisation du problème d'affectation quadratique (Quadratic Assignment Problem [QAP]). Pour l'affectation de valeurs aux arcs, nous proposons une approche de perturbation graduelle, afin de chercher la meilleure combinaison du coût de l'affectation, ceci en respectant certains paramètres comme la température, la dissipation de chaleur, la consommation d'énergie et la surface occupée par la puce. Le but ultime de ce travail est de proposer aux architectes de systèmes multiprocesseurs sur puce une méthodologie non traditionnelle et un outil systématique et efficace d'aide à la conception dès la phase de la spécification fonctionnelle du système.

Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it

Implementação da técnica de software pipelining na rede em chip IPNoSyS

Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Adaptive Routing Approaches for Networked Many-Core Systems

Through advances in technology, System-on-Chip design is moving towards integrating tens to hundreds of intellectual property blocks into a single chip. In such a many-core system, on-chip communication becomes a performance bottleneck for high performance designs. Network-on-Chip (NoC) has emerged as a viable solution for the communication challenges in highly complex chips. The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and NoC schemes provide the possibility of designing a high performance system in a limited chip area. The major advantages of 3D NoCs are the considerable reductions in average latency and power consumption. There are several factors degrading the performance of NoCs. In this thesis, we investigate three main performance-limiting factors: network congestion, faults, and the lack of efficient multicast support. We address these issues by the means of routing algorithms. Congestion of data packets may lead to increased network latency and power consumption. Thus, we propose three different approaches for alleviating such congestion in the network. The first approach is based on measuring the congestion information in different regions of the network, distributing the information over the network, and utilizing this information when making a routing decision. The second approach employs a learning method to dynamically find the less congested routes according to the underlying traffic. The third approach is based on a fuzzy-logic technique to perform better routing decisions when traffic information of different routes is available. Faults affect performance significantly, as then packets should take longer paths in order to be routed around the faults, which in turn increases congestion around the faulty regions. We propose four methods to tolerate faults at the link and switch level by using only the shortest paths as long as such path exists. The unique characteristic among these methods is the toleration of faults while also maintaining the performance of NoCs. To the best of our knowledge, these algorithms are the first approaches to bypassing faults prior to reaching them while avoiding unnecessary misrouting of packets. Current implementations of multicast communication result in a significant performance loss for unicast traffic. This is due to the fact that the routing rules of multicast packets limit the adaptivity of unicast packets. We present an approach in which both unicast and multicast packets can be efficiently routed within the network. While suggesting a more efficient multicast support, the proposed approach does not affect the performance of unicast routing at all. In addition, in order to reduce the overall path length of multicast packets, we present several partitioning methods along with their analytical models for latency measurement. This approach is discussed in the context of 3D mesh networks.

Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.

Redes-em-chip de baixo custo

Com as recentes tecnologias de fabricação é possível integrar milhões de transistores em um único chip, permitindo a criação dos chamados System-on-Chip (SoCs), que integram em um único chip um grande número de componentes (tipicamente blocos reutilizáveis conhecidos por núcleos). Quanto mais complexos forem estes sistemas, melhores técnicas de projeto serão necessárias para também reduzir o tempo e custo do projeto. Uma destas técnicas, chamada de Network-on-Chip (NoC), permite melhorar a performance da comunicação entre os núcleos e, ao mesmo tempo, fornecer uma plataforma de comunicação escalável e que pode ser reutilizada para um grande número de sistemas. Uma NoC pode ser definida como uma estrutura de roteadores e canais ponto-a-ponto que interconectam os núcleos de um sistema, provendo o suporte de comunicação entre eles. Os dados são transmitidos pela rede na forma de mensagens, que podem ser divididas em unidades menores chamadas de pacote. Uma das desvantagens desta plataforma de comunicação é o impacto na área do sistema causado pelos roteadores. Dentro deste contexto, este trabalho apresenta uma arquitetura de roteador de baixo custo, com o objetivo de permitir o uso de NoCs em sistemas onde a área do roteador representará um grande impacto no custo do sistema. A arquitetura deste roteador, chamado de Tonga, é baseada em um roteador chamado RASoC, um soft-core para SoCs. Nesta dissertação será apresentada também uma rede heterogênea, baseada na rede SoCIN, e composta por dois tipos de roteadores – RASoC e Tonga. Estes roteadores visam diferentes objetivos: Rasoc alcança uma maior performance comparada ao Tonga, mas ocupa área consideravelmente maior. Potencialmente, uma NoC heterogênea otimizada pode ser desenvolvida combinando estes roteadores, procurando o melhor compromisso entre área e latência. Os modelos desenvolvidos permitem a estimativa de área e do desempenho das arquiteturas de comunicação propostas e são apresentados resultados de performance para algumas aplicações.

The use of flow control devices to improve the flow pattern and throughput of sieve trays

Compared to packings trays are more cost effective column internals because they create a large interfacial area for mass transfer by the interaction of the vapour on the liquid. The tray supports a mass of froth or spray which on most trays (including the most widely used sieve trays) is not in any way controlled. The two important results of the gas/liquid interaction are the tray efficiency and the tray throughput or capacity. After many years of practical experience, both may be predicted by empirical correlations, despite the lack of understanding. It is known that the tray efficiency is in part determined by the liquid flow pattern and the throughput by the liquid froth height which in turn depends on the liquid hold-up and vapour velocity. This thesis describes experimental work on sieve trays in an air-water simulator, 2.44 m in diameter. The liquid flow pattern, for flow rates similar to those used in commercial scale distillation, was observed experimentally by direct observation; by water-cooling, to simulate mass transfer; use of potassium permanganate dye to observe areas of longer residence time; and by height of clear liquid measurements across the tray and in the downcomer using manometers. This work presents experiments designed to evaluate flow control devices proposed to improve the gas liquid interaction and hence improve the tray efficiency and throughput. These are (a) the use of intermediate weirs to redirect liquid to the sides of the tray so as to remove slow moving/stagnant liquid and (b) the use of vapour-directing slots designed to use the vapour to cause liquid to be directed towards the outlet weir thus reducing the liquid hold-up at a given rate i.e. increased throughput. This method also has the advantage of removing slow moving/stagnant liquid. In the experiments using intermediate weirs, which were placed in the centre of the tray. it was found that in general the effect of an intermediate weir depends on the depth of liquid downstream of the weir. If the weir is deeper than the downstream depth it will cause the upstream liquid to be deeper than the downstream liquid. If the weir is not as deep as deep as the downstream depth it may have little or no effect on the upstream depth. An intermediate weir placed at an angle to the direction of flow of liquid increases the liquid towards the sides of the tray without causing an increase in liquid hold-up/ froth height. The maximum proportion of liquid caused to flow sideways by the weir is between 5% and 10%. Experimental work using vapour-directing slots on a rectangular sieve tray has shown that the horizontal momentum that is imparted to the liquid is dependent upon the size of the slot. If too much momentum is transferred to the liquid it causes hydraulic jumps to occur at the mouth of the slot coupled with liquid being entrained, The use of slots also helps to eliminate the hydraulic gradient across sieve trays and provides a more uniform froth height on the tray. By comparing the results obtained of the tray and point efficiencies, it is shown that a slotted tray reduces both values by approximately 10%. This reduction is due to the fact that with a slotted tray the liquid has a reduced residence time Ion the tray coupled also with the fact that large size bubbles are passing through the slots. The effectiveness of using vapour-directing slots on a full circular tray was investigated by using dye to completely colour the biphase. The removal of the dye by clear liquid entering the tray was monitored using an overhead camera. Results obtained show that the slots are successful in their aim of reducing slow moving liquid from the sides of the tray, The net effect of this is an increase in tray efficiency. Measurements of slot vapour-velocity found it to be approximately equal to the hole velocity.

Comunicações intra- e inter-circuito de componentes especificados com Redes de Petri

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levels

Phase voltage control and filtering in a converter-fed single-phase customer-end system of the LVDC distribution network

In recent years, the network vulnerability to natural hazards has been noticed. Moreover, operating on the limits of the network transmission capabilities have resulted in major outages during the past decade. One of the reasons for operating on these limits is that the network has become outdated. Therefore, new technical solutions are studied that could provide more reliable and more energy efficient power distributionand also a better profitability for the network owner. It is the development and price of power electronics that have made the DC distribution an attractive alternative again. In this doctoral thesis, one type of a low-voltage DC distribution system is investigated. Morespecifically, it is studied which current technological solutions, used at the customer-end, could provide better power quality for the customer when compared with the current system. To study the effect of a DC network on the customer-end power quality, a bipolar DC network model is derived. The model can also be used to identify the supply parameters when the V/kW ratio is approximately known. Although the model provides knowledge of the average behavior, it is shown that the instantaneous DC voltage ripple should be limited. The guidelines to choose an appropriate capacitance value for the capacitor located at the input DC terminals of the customer-end are given. Also the structure of the customer-end is considered. A comparison between the most common solutions is made based on their cost, energy efficiency, and reliability. In the comparison, special attention is paid to the passive filtering solutions since the filter is considered a crucial element when the lifetime expenses are determined. It is found out that the filter topology most commonly used today, namely the LC filter, does not provide economical advantage over the hybrid filter structure. Finally, some of the typical control system solutions are introduced and their shortcomings are presented. As a solution to the customer-end voltage regulation problem, an observer-based control scheme is proposed. It is shown how different control system structures affect the performance. The performance meeting the requirements is achieved by using only one output measurement, when operating in a rigid network. Similar performance can be achieved in a weak grid by DC voltage measurement. An additional improvement can be achieved when an adaptive gain scheduling-based control is introduced. As a conclusion, the final power quality is determined by a sum of various factors, and the thesis provides the guidelines for designing the system that improves the power quality experienced by the customer.

Clinical outcomes of kidney transplants on patients with end-stage renal disease secondary to lupus nephritis, polycystic kidney disease and diabetic nephropathy

Background: Patients with lupus nephritis could progress to endstage renal disease (10-22%); hence, kidney transplants should be considered as the treatment of choice for these patients. Objective: To evaluate the clinical outcomes after kidney transplants in patients with chronic kidney diseases secondary to lupus nephritis, polycystic kidney disease and diabetes nephropathy at Pablo Tobon Uribe Hospital. Methods: A descriptive and retrospective study performed at one kidney transplant center between 2005 and 2013. Results: A total of 136 patients, 27 with lupus nephritis (19.9%), 31 with polycystic kidney disease (22.8%) and 78 with diabetes nephropathy (57.4%), were included in the study. The graft survivals after one, three and five years were 96.3%, 82.5% and 82.5% for lupus nephritis; 90%, 86% and 76.5% for polycystic kidney disease and 91.7%, 80.3% and 67.9% for diabetes nephropathy, respectively, with no significant differences (p= 0.488); the rate of lupus nephritis recurrence was 0.94%/person-year. The etiology of lupus vs diabetes vs polycystic disease was not a risk factor for a decreased time of graft survival (Hazard ratio: 1.43; 95% CI: 0.52-3.93). Conclusion: Kidney transplant patients with end stage renal disease secondary to lupus nephritis has similar graft and patient survival success rates to patients with other kidney diseases. The complication rate and risk of recurrence for lupus nephritis are low. Kidney transplants should be considered as the treatment of choice for patients with end stage renal disease secondary to lupus nephritis.

Early Effects on T lymphocyte Response to Iron Deficiency in Mice. Short Communication

Iron deficiency is a common nutritional disorder, affecting about 30% of the world population. Deficits in iron functional compartments have suppressive effects on the immune system. Environmental problems, age, and other nutrient deficiencies are some of the situations which make human studies difficult and warrant the use of animal models. This study aimed to investigate alterations in the immune system by inducing iron deficiency and promoting recuperation in a mouse model. Hemoglobin concentration, hematocrit, liver iron store, and flow cytometry analyses of cell-surface transferrin receptor (CD71) on peripheral blood and spleen CD4+ and CD8+ T lymphocyte were performed in the control (C) and the iron-deficient (ID) groups of animals at the beginning and end of the experiment. Hematological indices of C and ID mice were not different but the iron stores of ID mice were significantly reduced. Although T cell subsets were not altered, the percentage of T cells expressing CD71 was significantly increased by ID. The results suggest that iron deficiency induced by our experimental model would mimic the early events in the onset of anemia, where thymus atrophy is not enough to influence subset composition of T cells, which can still respond to iron deficiency by upregulating the expression of transferrin receptor.